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130 lines
3.3 KiB
130 lines
3.3 KiB
#include <stdio.h> |
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#include "fpga_cell.h" |
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#include "fpga_fdef_loader.h" |
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#include "fpga_global.h" |
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#include "fpga.h" |
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#include "unistd.h" |
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#include "string.h" |
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#include "fpga_cell_lut34.h" /* For testing purposes only */ |
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#define E_FDEF 1 |
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#define E_BITSTREAM 2 |
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static void test_design_cell_ripple(struct fpga_cell_lut34 *cell, int first, int last) |
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{ |
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cell->lut_in_sel[0] = LUT_NET_F0; // Own state |
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cell->lut_in_sel[1] = LUT_NET_F2; // Feedback &-net -- just for fun |
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cell->lut_in_sel[2] = (first ? LUT_NET_T2 : LUT_NET_L1); // &-state of previous stages |
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cell->lut_in_sel[3] = LUT_NET_L0; // Previous state -- just for fun |
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cell->sync = 1; |
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cell->drive_sel[0] = 'A'; |
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cell->drive_sel[1] = 'b'; |
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cell->drive_sel[2] = (last ? 'b' : 'Z'); |
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cell->drive_sel[3] = 'Z'; |
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cell->route_en = (1 << ROUTE_L2); |
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cell->LUT3[0] = 0b01011010; |
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cell->LUT3[1] = 0b10100000; |
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} |
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// WARNING: Requires a >=4x4 FPGA FDEF! |
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static void test_design_counter(struct fpga_cell *entry_cell) |
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{ |
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struct fpga_cell_lut34 *cell; |
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int i, j; |
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for (i = 0; i < 4; ++i) { |
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cell = ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT])); |
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for (j = 4 - i; j < 4; ++j) { |
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cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[BOTTOM]; |
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} |
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test_design_cell_ripple(cell, 1, 0); |
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cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT]; |
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test_design_cell_ripple(cell, 0, 0); |
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cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT]; |
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test_design_cell_ripple(cell, 0, 0); |
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cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT]; |
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test_design_cell_ripple(cell, 0, 1); |
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} |
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} |
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int development_test_main(int argc, char *argv[]) |
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{ |
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struct fpga_cell *entry_cell; |
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struct fpga_chain *chain; |
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int opt; |
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char *fdef_filename = "fdef/4x4.fdef"; |
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char *kst_filename = "-"; |
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char *bitstream_filename = "-"; |
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int bitstream_ascii = 0; |
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set_log_level(LL_DEBUG); |
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while((opt = getopt(argc, argv, "f:i:o:h")) != -1) |
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{ |
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switch(opt) |
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{ |
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case 'f': |
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fdef_filename = optarg; |
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break; |
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case 'i': |
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kst_filename = optarg; |
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report(LL_WARNING, "Input not yet implemented."); |
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break; |
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case 'o': |
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bitstream_filename = optarg; |
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break; |
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case 'h': |
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bitstream_ascii = 1; |
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break; |
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case ':': |
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case '?': |
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printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n" |
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"Generate bitstreams for the TTL-FPGA.\n\n" |
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"When INPUT or OUTPUT is -, read/write standard input.\n\n" |
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" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n" |
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" -i\tKousaten input file, default stdin\n" |
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" -o\tOutput file, default stdout\n" |
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" -h\tGenerate output as ASCII HEX\n", |
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argv[0]); |
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return 0; |
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default: |
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break; |
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} |
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} |
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entry_cell = fpga_fdef_loader_load(fdef_filename); |
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if (!entry_cell) { |
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report(LL_CRITICAL, "Error loading FDEF."); |
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return E_FDEF; |
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} |
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report(LL_INFO, "FDEF loaded."); |
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chain = fpga_isp_chain_new(entry_cell); |
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if (!chain) { |
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report(LL_CRITICAL, "Critical error during bitstream generation."); |
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return E_BITSTREAM; |
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} |
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report(LL_INFO, "Chain loaded."); |
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test_design_counter(entry_cell); |
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if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) { |
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report(LL_ERROR, "Bitstream generation failed."); |
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return E_BITSTREAM; |
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} |
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report(LL_INFO, "Generated bitstream."); |
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return 0; |
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} |
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int main(int argc, char *argv[]) |
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{ |
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return development_test_main(argc, argv); |
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}
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