31 lines
978 B
VHDL
31 lines
978 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package fifo_package is
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component fifo is
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generic(
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sync_depth : natural := 3;
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gray_code : boolean := true;
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addr_width : natural := 4;
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data_width : natural := 32);
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port(
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rst : in std_logic;
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-- write port, only set w_en when w_rdy
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w_clk : in std_logic;
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w_rdy : out std_logic;
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w_en : in std_logic;
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w_data : in std_logic_vector(data_width-1 downto 0);
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-- (pre)alloc port, can be unused
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a_clk : in std_logic;
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a_rdy : out std_logic;
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a_en : in std_logic;
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-- read port, only set r_en when r_rdy
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-- data is valid the cycle after r_en raised
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r_clk : in std_logic;
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r_rdy : out std_logic;
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r_en : in std_logic;
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r_data : out std_logic_vector(data_width-1 downto 0));
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end component;
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end fifo_package;
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