mor1kx-bemicrocv/ip/intercon/rtl/fifo_package.vhd

31 lines
978 B
VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package fifo_package is
component fifo is
generic(
sync_depth : natural := 3;
gray_code : boolean := true;
addr_width : natural := 4;
data_width : natural := 32);
port(
rst : in std_logic;
-- write port, only set w_en when w_rdy
w_clk : in std_logic;
w_rdy : out std_logic;
w_en : in std_logic;
w_data : in std_logic_vector(data_width-1 downto 0);
-- (pre)alloc port, can be unused
a_clk : in std_logic;
a_rdy : out std_logic;
a_en : in std_logic;
-- read port, only set r_en when r_rdy
-- data is valid the cycle after r_en raised
r_clk : in std_logic;
r_rdy : out std_logic;
r_en : in std_logic;
r_data : out std_logic_vector(data_width-1 downto 0));
end component;
end fifo_package;