21 lines
475 B
VHDL
21 lines
475 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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package test_slave_package is
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component test_slave is
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generic(
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delay : integer := 1
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);
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port(
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-- Common wishbone signals
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clk : in std_logic;
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rst : in std_logic;
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-- Slave control port
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slave_i : in wishbone_slave_in;
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slave_o : out wishbone_slave_out
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);
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end component;
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end test_slave_package;
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