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flashrom: Added code to enforce a cs inactive delay between SPI transactions

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This commit is contained in:
Markus Koch 2016-12-05 20:35:35 +01:00
parent 9ff7421242
commit 202df5380b
1 changed files with 23 additions and 13 deletions
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36
cores/flashrom-wb/flashrom_spi.vhd
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@ -45,6 +45,7 @@ architecture RTL of flashrom_spi is
signal oneBitRead : std_logic; signal oneBitRead : std_logic;
signal pseudoEdge : boolean; signal pseudoEdge : boolean;
signal dummy_passed : boolean; signal dummy_passed : boolean;
signal prevent_retrig : boolean;
begin begin
toSpi : process(clk, rst) is toSpi : process(clk, rst) is
procedure default_state is procedure default_state is
@ -77,20 +78,28 @@ begin
else else
case state is case state is
when IDLE => when IDLE =>
delayCycle <= '0'; prevent_retrig <= false;
spi_sck <= '0'; delayCycle <= '0';
oneBitRead <= '0'; spi_sck <= '0';
dummy_passed <= false; oneBitRead <= '0';
data_out <= (others => '0'); dummy_passed <= false;
if data_in_valid = '1' then data_out <= (others => '0');
state <= TX; if ckDiv = clk_divider - 2 then -- ensures cs inactive time between transactions
bitCounter <= 0; if data_in_valid = '1' then
bitCounterIn <= 0; ckDiv <= 0;
data_in_length_i <= 0; state <= TX;
pseudoEdge <= true; bitCounter <= 0;
bitCounterIn <= 0;
data_in_length_i <= 0;
pseudoEdge <= true;
end if;
else
ckDiv <= ckDiv + 1;
end if; end if;
ckDiv <= 0;
when TX => when TX =>
if data_in_valid = '0' then
prevent_retrig <= true;
end if;
if ckDiv = clk_divider - 2 or pseudoEdge then if ckDiv = clk_divider - 2 or pseudoEdge then
ckDiv <= 0; ckDiv <= 0;
if not pseudoEdge then if not pseudoEdge then
@ -104,7 +113,7 @@ begin
if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data
if bitCounter = data_in_length_i then if bitCounter = data_in_length_i then
bitCounter <= 0; bitCounter <= 0;
if data_in_valid = '1' then if data_in_valid = '1' and not prevent_retrig then
shiftreg <= data_in; shiftreg <= data_in;
data_in_length_i <= data_in_length - 1; data_in_length_i <= data_in_length - 1;
data_out_length_i <= data_out_length - 1; data_out_length_i <= data_out_length - 1;
@ -140,6 +149,7 @@ begin
if delayCycle = '1' then if delayCycle = '1' then
spi_sck <= '0'; spi_sck <= '0';
state <= IDLE; state <= IDLE;
ckDiv <= 0;
end if; end if;
end if; end if;
end if; end if;