fpga/mor1kx-bemicrocv
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Added UART to top level

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This commit is contained in:
Markus Koch 2017-03-02 09:30:38 +01:00
parent 4ca1ba0928
commit 20387479c0
1 changed files with 21 additions and 4 deletions
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25
design/top.vhd
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@ -59,12 +59,12 @@ architecture RTL of top is
-- WB config -- WB config
constant masters : natural := 3; constant masters : natural := 3;
constant slaves : natural := 4; constant slaves : natural := 5;
constant INTERCON_ID_SRAM : natural := 0; constant INTERCON_ID_SRAM : natural := 0;
constant INTERCON_ID_DDR3 : natural := 1; constant INTERCON_ID_DDR3 : natural := 1;
constant INTERCON_ID_FLASH : natural := 2; constant INTERCON_ID_FLASH : natural := 2;
constant INTERCON_ID_GPIO : natural := 3; constant INTERCON_ID_GPIO : natural := 3;
-- constant INTERCON_ID_UART : natural := 3; constant INTERCON_ID_UART : natural := 4;
-- constant INTERCON_ID_NS16550 : natural := 4; -- constant INTERCON_ID_NS16550 : natural := 4;
constant in_simulation : boolean := false constant in_simulation : boolean := false
@ -333,6 +333,21 @@ begin
gpio => GPIOA gpio => GPIOA
); );
-- UART
uart_wb_inst : entity work.uart_wb
generic map(
portcount => 1
)
port map(
clk => clk,
rst => rst,
slave_i => intercon_slave_i(INTERCON_ID_UART),
slave_o => intercon_slave_o(INTERCON_ID_UART),
irq_o => open, -- TODO
rx(0) => uart_rx,
tx(0) => uart_tx
);
-- Intercon -- Intercon
crossbar_inst : entity ip.crossbar crossbar_inst : entity ip.crossbar
generic map( generic map(
@ -351,13 +366,15 @@ begin
INTERCON_ID_SRAM => x"00000000", INTERCON_ID_SRAM => x"00000000",
INTERCON_ID_DDR3 => x"10000000", INTERCON_ID_DDR3 => x"10000000",
INTERCON_ID_FLASH => x"40000000", INTERCON_ID_FLASH => x"40000000",
INTERCON_ID_GPIO => x"80000000" INTERCON_ID_GPIO => x"80000000",
INTERCON_ID_UART => x"80000100"
), ),
mask => ( mask => (
INTERCON_ID_SRAM => x"ffff0000", INTERCON_ID_SRAM => x"ffff0000",
INTERCON_ID_DDR3 => x"f0000000", INTERCON_ID_DDR3 => x"f0000000",
INTERCON_ID_FLASH => x"f0000000", INTERCON_ID_FLASH => x"f0000000",
INTERCON_ID_GPIO => x"fffffffc" INTERCON_ID_GPIO => x"fffffff0",
INTERCON_ID_UART => x"ffffffc0"
) )
); );
end architecture RTL; end architecture RTL;