Extended top test bench

This commit is contained in:
Markus Koch 2017-02-26 20:40:29 +01:00
parent dfcd35b152
commit b48571db24
1 changed files with 79 additions and 47 deletions

View File

@ -36,6 +36,15 @@ architecture RTL of bench_top is
signal mem_dqs_n : std_logic_vector(1 downto 0);
signal mem_odt : std_logic_vector(0 downto 0);
signal oct_rzqin : std_logic;
-- Flash
signal flash_si : std_logic;
signal flash_cs_n : std_logic;
signal flash_sck : std_logic;
signal flash_wp_n : std_logic;
signal flash_reset_n : std_logic;
signal flash_so : std_logic;
signal flash_busy : std_logic;
begin
top_inst : entity design.top
port map(
@ -61,7 +70,30 @@ begin
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => mem_odt,
oct_rzqin => oct_rzqin
oct_rzqin => oct_rzqin,
flash_si => flash_si,
flash_so => flash_so,
flash_sck => flash_sck,
flash_reset_n => flash_reset_n,
flash_cs_n => flash_cs_n,
flash_wp_n => flash_wp_n
);
DataFlash_inst : entity work.DataFlash
generic map(
flashmemory => "devicemodels/memory.txt",
Rapid_interface => true,
fsck => 66,
DEVICE => "AT45DB011D", --AT45DB011D
Tsck => 13.6 ns)
port map(
SI => flash_si,
CSB => flash_cs_n,
SCK => flash_sck,
WPB => flash_wp_n,
RESETB => flash_reset_n,
SO => flash_so,
RDYBSY => flash_busy
);
clock_driver : process