fpga/mor1kx-bemicrocv
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Added page read (incomplete)

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This commit is contained in:
Markus Koch 2016-12-05 20:37:04 +01:00
parent 202df5380b
commit c38d926569
3 changed files with 61 additions and 12 deletions
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48
bench/bench_flashrom_controller.vhd
View File

@ -107,8 +107,11 @@ begin
--testbench --testbench
bench : process is bench : process is
begin begin
rst <= '1'; rst <= '1';
clr <= '0'; clr <= '0';
status_update_stb <= '0';
load_stb <= '0';
page <= (others => '0');
wait for 10 ns * 2; wait for 10 ns * 2;
wait until (rising_edge(clk)); wait until (rising_edge(clk));
rst <= '0'; rst <= '0';
@ -117,7 +120,10 @@ begin
-- bench code here -- bench code here
wait until ready = '1'; wait until ready = '1';
strobe(load_stb); strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1'; wait until ready = '1';
strobe(load_stb); strobe(load_stb);
@ -132,7 +138,41 @@ begin
strobe(status_update_stb); strobe(status_update_stb);
wait until ready = '1'; wait until ready = '1';
strobe(load_stb); strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait; wait;
end process bench; end process bench;

24
cores/flashrom-wb/flashrom_controller.vhd
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@ -37,10 +37,10 @@ end entity flashrom_controller;
architecture RTL of flashrom_controller is architecture RTL of flashrom_controller is
constant spif_max_word_length : integer := 32; constant spif_max_word_length : integer := 32;
constant max_dummy_bits : integer := 16; constant max_dummy_bits : integer := 63;
constant bootup_delay : integer := 4000; constant bootup_delay : integer := 4000;
type state_t is (INIT, GETINFO, GETSTATUS, IDLE); type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, IDLE);
signal state : state_t; signal state : state_t;
signal spif_data_in_valid : std_logic; signal spif_data_in_valid : std_logic;
@ -106,13 +106,13 @@ begin
temp_cnt := 0; temp_cnt := 0;
end procedure reset_state; end procedure reset_state;
procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector(31 downto 0)) is procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector) is
begin begin
spif_data_in_length <= data_in_length; spif_data_in_length <= data_in_length;
spif_data_out_length <= data_out_length; spif_data_out_length <= data_out_length;
spif_data_out_dummy_bits <= data_out_dummy_bits; spif_data_out_dummy_bits <= data_out_dummy_bits;
spif_data_in_valid <= '1'; spif_data_in_valid <= '1';
spif_data_in <= data_in; spif_data_in <= data_in & padBits(spif_data_in, data_in);
if temp_cnt = nTxWords then if temp_cnt = nTxWords then
spif_data_in_valid <= '0'; spif_data_in_valid <= '0';
@ -120,7 +120,7 @@ begin
temp_cnt := temp_cnt + 1; temp_cnt := temp_cnt + 1;
end if; end if;
if spif_data_out_valid = '1' then if spif_data_out_valid = '1' and (temp_cnt = nTxWords) then
spif_data_in_valid <= '0'; spif_data_in_valid <= '0';
done := true; done := true;
state <= IDLE; state <= IDLE;
@ -146,7 +146,7 @@ begin
temp_cnt := temp_cnt + 1; temp_cnt := temp_cnt + 1;
end if; end if;
when GETINFO => -- TODO: In simulation I can only call this command once?! when GETINFO => -- TODO: In simulation I can only call this command once?!
run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID)); run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID);
if done then if done then
info <= spif_data_out; info <= spif_data_out;
end if; end if;
@ -156,16 +156,24 @@ begin
state <= GETSTATUS; state <= GETSTATUS;
end if; end if;
if load_stb = '1' then --debug only if load_stb = '1' then --debug only
state <= GETINFO; state <= LOADPAGE;
end if; end if;
when GETSTATUS => when GETSTATUS =>
run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS)); run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS);
if done then if done then
status <= spif_data_out(7 downto 0); status <= spif_data_out(7 downto 0);
end if; end if;
when LOADPAGE =>
run_command_single(24, 8, 34, 16, FLASHROM_COMMAND_CONT_ARRAY_READ & page);
if done then
report "Load page done." severity note;
end if;
end case; end case;
end if; end if;
end if; end if;
end process flashrom_controller_p; end process flashrom_controller_p;
ready <= '1' when state = IDLE else '0'; ready <= '1' when state = IDLE else '0';
data_out <= spif_data_out(7 downto 0);
data_out_valid <= spif_data_out_valid when state = LOADPAGE else '0';
end architecture RTL; end architecture RTL;

1
cores/flashrom-wb/flashrom_pkg.vhd
View File

@ -6,6 +6,7 @@ package flashrom_pkg is
constant FLASHROM_ADDR_WIDTH : integer := 12; constant FLASHROM_ADDR_WIDTH : integer := 12;
constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7"; constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7";
constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B";
function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector;
end package flashrom_pkg; end package flashrom_pkg;