|  | cbda2c1302 | Corrected bit count for readpage (now works on real HW) | 2017-02-26 20:38:29 +01:00 |  | 
			
				
					|  | d3b2ea88b5 | Fixed bug in flashrom_spi causing the clock to be active for too long | 2017-02-26 18:30:25 +01:00 |  | 
			
				
					|  | d33b027e28 | Added CS inactive delay + some other fixes | 2017-02-26 15:13:19 +01:00 |  | 
			
				
					|  | e053da3ae1 | flashrom: Added Wishbone controller | 2016-12-10 20:51:00 +01:00 |  | 
			
				
					|  | 9051e3385b | flashrom: Minor changes | 2016-12-10 20:50:03 +01:00 |  | 
			
				
					|  | 054ae0e210 | flashrom: Added wait-not-busy after write | 2016-12-06 21:24:09 +01:00 |  | 
			
				
					|  | 265d1a80e1 | flashrom: Added write command, fixed read command | 2016-12-06 19:53:39 +01:00 |  | 
			
				
					|  | f55d735855 | flashrom: Changed read count | 2016-12-06 16:47:31 +01:00 |  | 
			
				
					|  | c38d926569 | Added page read (incomplete) | 2016-12-05 20:37:04 +01:00 |  | 
			
				
					|  | 202df5380b | flashrom: Added code to enforce a cs inactive delay between SPI transactions | 2016-12-05 20:35:35 +01:00 |  | 
			
				
					|  | 9ff7421242 | flashrom: Cleanup | 2016-12-04 18:27:58 +01:00 |  | 
			
				
					|  | 5ad7677b3a | flashrom: Added GETSTATUS command | 2016-12-04 18:00:31 +01:00 |  | 
			
				
					|  | e66c98a670 | flashrom: Transmitted one clock cycle too long -> buffer shifted | 2016-12-04 17:58:27 +01:00 |  | 
			
				
					|  | 9b379e70fe | flashrom: Changed SPI core to conform to DataFlash behavior, changed main fsm to request the right number of transactions | 2016-08-04 20:59:43 +02:00 |  | 
			
				
					|  | a1efcf62c4 | Initial commit | 2016-08-04 19:22:38 +02:00 |  |