35 lines
1.0 KiB
VHDL
35 lines
1.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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package dma_package is
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component dma is
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generic(
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-- Value 0 cannot stream
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-- Value 1 only slaves with async ACK can stream
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-- Value 2 only slaves with combined latency <= 2 can stream
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-- Value 3 only slaves with combined latency <= 6 can stream
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-- Value 4 only slaves with combined latency <= 14 can stream
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-- ....
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logRingLen : integer := 4
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);
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port(
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-- Common wishbone signals
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clk : in std_logic;
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rst : in std_logic;
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-- Slave control port
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slave_i : in wishbone_slave_in;
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slave_o : out wishbone_slave_out;
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-- Master reader port
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r_master_i : in wishbone_master_in;
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r_master_o : out wishbone_master_out;
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-- Master writer port
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w_master_i : in wishbone_master_in;
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w_master_o : out wishbone_master_out;
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-- Pulsed high completion signal
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interrupt : out std_logic
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);
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end component;
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end dma_package;
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