106 lines
2.3 KiB
VHDL
106 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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entity bench_top is
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end entity bench_top;
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architecture RTL of bench_top is
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constant SIM_SPEEDUP : natural := 2;
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signal clk_hw : std_logic;
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signal rst_hw : std_logic;
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signal ws2812_out : std_logic_vector(4 - 1 downto 0);
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signal uart_tx : std_logic;
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begin
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top_inst : entity design.top
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generic map(
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f_clk => 24_000_000 / SIM_SPEEDUP,
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ROWS => 4,
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COLUMNS => 4
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)
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port map(
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clk_hw => clk_hw,
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rst_hw => rst_hw,
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ws2812_out => ws2812_out,
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uart_rx => uart_tx
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);
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clock_driver : process
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constant period : time := (1 sec / 24_000_000);
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begin
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clk_hw <= '0';
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wait for period / 2;
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clk_hw <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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constant UART_BITTIME : time := 1 sec / 115200 / SIM_SPEEDUP;
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procedure uart_transmit(data : in std_logic_vector(7 downto 0)) is
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begin
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uart_tx <= '0';
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wait for UART_BITTIME;
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for i in 0 to 7 loop
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uart_tx <= data(i);
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wait for UART_BITTIME;
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end loop;
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uart_tx <= '1';
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wait for UART_BITTIME;
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end procedure uart_transmit;
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begin
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rst_hw <= '0';
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uart_tx <= '1';
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wait until clk_hw = '1';
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wait until clk_hw = '1';
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rst_hw <= '1';
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wait until clk_hw = '1';
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wait for UART_BITTIME * 13;
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wait until clk_hw = '1';
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-- Write LED data (cmd 0x00)
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uart_transmit(x"00");
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uart_transmit(x"00"); -- Start address 0
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uart_transmit(x"00");
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uart_transmit(x"00"); -- Write two LEDs
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uart_transmit(x"02");
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uart_transmit(x"01"); -- First LED
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uart_transmit(x"02");
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uart_transmit(x"03");
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uart_transmit(x"11");
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uart_transmit(x"12");
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uart_transmit(x"13");
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uart_transmit(x"21");
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uart_transmit(x"22");
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uart_transmit(x"23");
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uart_transmit(x"31");
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uart_transmit(x"32");
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uart_transmit(x"33");
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uart_transmit(x"a1"); -- Second LED
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uart_transmit(x"a2");
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uart_transmit(x"a3");
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uart_transmit(x"b1");
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uart_transmit(x"b2");
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uart_transmit(x"b3");
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uart_transmit(x"c1");
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uart_transmit(x"c2");
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uart_transmit(x"c3");
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uart_transmit(x"d1");
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uart_transmit(x"d2");
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uart_transmit(x"d3");
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-- Render (cmd 0x01)
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uart_transmit(x"01");
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wait;
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end process test;
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end architecture RTL;
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