37 lines
985 B
VHDL
37 lines
985 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ram is
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generic(
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WIDTH : natural := 8;
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DEPTH : natural := 4
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);
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port(
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clk : in std_logic;
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addr_a : in std_logic_vector(DEPTH - 1 downto 0);
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data_out_a : out std_logic_vector(WIDTH - 1 downto 0);
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data_in_a : in std_logic_vector(WIDTH - 1 downto 0);
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we_a : in std_logic;
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addr_b : in std_logic_vector(DEPTH - 1 downto 0);
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data_out_b : out std_logic_vector(WIDTH - 1 downto 0)
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);
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end entity ram;
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architecture rtl of ram is
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type memory_t is array (0 to integer(2**DEPTH) - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal memory : memory_t;
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begin
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ram_p : process(clk) is
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begin
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if (rising_edge(clk)) then
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data_out_a <= memory(to_integer(unsigned(addr_a)));
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if (we_a = '1') then
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memory(to_integer(unsigned(addr_a))) <= data_in_a;
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end if;
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data_out_b <= memory(to_integer(unsigned(addr_b)));
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end if;
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end process ram_p;
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end architecture rtl;
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