trashernet/bench/bench_trashernet_mac.vhd

-- -------------------------------------------------------------------------- --
--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
-- -------------------------------------------------------------------------- --
-- bench_trashernet_mac.vhd : Stimulus-only test bench for the MAC+PHY parts
--   Tests TX path through the RX path. Not great, but whatever.
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.bench_pkg.all;

library trashernet;
use trashernet.trashernet_pkg.all;

library vunit_lib;
context vunit_lib.vunit_context;

entity bench_trashernet_mac is
	generic(
		runner_cfg : string
	);
end entity bench_trashernet_mac;

architecture bench of bench_trashernet_mac is
	signal clk     : std_logic;
	signal phy_clk : std_logic;
	signal rst     : std_logic;

	signal phy_out : phy_out_t;
	signal phy_in  : phy_in_t;
	signal rx_p    : std_logic;
	signal tx_p    : std_logic;
	signal tx_n    : std_logic;

	signal mac_out : mac_out_t;
	signal mac_in  : mac_in_t;

	constant TEST_BENCH_LOOPBACK : boolean := true;

	signal mac_tx_start : std_logic := '0';

begin
	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
		generic map(
			F_CLK     => 49000000,
			F_CLK_PHY => 100000000
		)
		port map(
			clk     => clk,
			phy_clk => phy_clk,
			rst     => rst,
			phy_out => phy_out,
			phy_in  => phy_in,
			rx_p    => rx_p,
			tx_p    => tx_p,
			tx_n    => tx_n
		);

	trashernet_mac_inst : entity trashernet.trashernet_mac
		port map(
			clk     => clk,
			rst     => rst,
			phy_out => phy_out,
			phy_in  => phy_in,
			mac_out => mac_out,
			mac_in  => mac_in
		);

	clock_driver : process
		constant period : time := 20 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	phy_clock_driver : process
		constant period : time := 10 ns;
	begin
		phy_clk <= '0';
		wait for period / 2;
		phy_clk <= '1';
		wait for period / 2;
	end process phy_clock_driver;

	rstsim : process is
	begin
		rst <= '1';
		wait for 20 ns;
		rst <= '0';
		wait for 20 ns;
		wait;
	end process rstsim;

	loopbackmode : if TEST_BENCH_LOOPBACK generate
		rx_p <= tx_p;
	else generate
		test : process is
		begin
			wait until rst = '0';
			wait for 10 ns;
			rx_p <= '0';

			send_data(rx_p, byte_vector'(
				x"55", x"55", x"55", x"D5",
				x"11", x"22", x"33", x"44", x"55", x"66", x"00", x"e0", x"4c", x"36", x"00", x"2f", x"08", x"00", x"45", x"00", x"00", x"54", x"fe", x"22", x"40", x"00", x"40", x"01", x"f5", x"28", x"c0", x"a8", x"63", x"0a", x"c0", x"a8", x"63", x"02", x"08", x"00", x"90", x"e6", x"00", x"06", x"00", x"01", x"da", x"bd", x"2c", x"61", x"00", x"00", x"00", x"00", x"9f", x"20", x"02", x"00", x"00", x"00", x"00", x"00", x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b", x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28", x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37",
				x"e9", x"f2", x"6b", x"30"
			));

			send_data(rx_p, byte_vector'(
				x"55", x"55", x"55", x"D5",
				x"11", x"22", x"33", x"44", x"55", x"66", x"00", x"e0", x"4c", x"36", x"00", x"2f", x"08", x"00", x"45", x"00", x"00", x"54", x"ca", x"78", x"40", x"00", x"40", x"01", x"28", x"d4", x"c0", x"a8", x"63", x"0a", x"c0", x"a8", x"63", x"01", x"08", x"00", x"93", x"f5", x"00", x"03", x"00", x"01", x"3c", x"bc", x"2c", x"61", x"00", x"00", x"00", x"00", x"38", x"16", x"04", x"00", x"00", x"00", x"00", x"00", x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b", x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28", x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37",
				x"b9", x"7f", x"c7", x"91"
			));

			send_data(rx_p, byte_vector'(
				x"55", x"55", x"55", x"D5",
				x"12", x"34", x"56", x"78", x"90", x"12",
				x"AB", x"CD", x"EF", x"AA", x"BB", x"CC",
				x"08", x"00",
				x"11", x"22", x"33", x"44", x"55", x"66",
				x"CC", x"2C", x"CC", x"2C"
			));

			wait;
		end process test;
	end generate loopbackmode;

	receiver : process is
	begin
		wait until rising_edge(clk);
		if phy_out.rx_data_valid then
			report "[PHY] RX byte: " & to_hstring(phy_out.rx_data);
		end if;
		if mac_out.rx_mac_valid then
			report "[MAC] RX byte: " & to_hstring(mac_out.rx_mac_data);
		end if;
		if mac_out.rx_mac_crc_ok then
			report "[MAC] RX CRC OK";
		end if;
		if mac_out.rx_mac_crc_error then
			report "[MAC] RX CRC error";
		end if;
	end process receiver;

	mac_tx : process is
	begin
		wait on mac_tx_start;

		mac_in.tx_mac_data               <= x"11";
		mac_in.tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
		mac_in.tx_header.mac_source      <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
		mac_in.tx_header.mac_ethertype   <= (x"01", x"00");
		mac_in.tx_mac_data_en            <= '0';

		wait until rst = '0';
		wait for 100 ns;

		mac_in.tx_mac_data_en <= '1';
		wait until rising_edge(mac_out.tx_mac_data_ack);
		wait until rising_edge(mac_out.tx_mac_data_ack);
		wait until rising_edge(mac_out.tx_mac_data_ack);
		wait until rising_edge(clk);
		mac_in.tx_mac_data_en <= '0';
	end process mac_tx;

	test : process is
	begin
		wait for 1 ns;

		test_runner_setup(runner, runner_cfg);

		while test_suite loop

			if run("mac_tx_rx_simple") then
				mac_tx_start <= not mac_tx_start;
				wait on mac_out.rx_mac_crc_ok, mac_out.rx_mac_crc_error for 1 ms;
				assert mac_out.rx_mac_crc_ok = '1' report "Did not receive CRC OK" severity error;
			end if;
		end loop;

		wait for 1 ns;
		wait until rising_edge(clk);

		test_runner_cleanup(runner);
	end process test;

end architecture bench;