mac: Refactor to use records for the application interface
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@ -32,16 +32,8 @@ architecture bench of bench_trashernet_mac is
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal rx_mac_data : byte;
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signal rx_mac_valid : std_logic;
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signal rx_mac_crc_ok : std_logic;
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signal rx_mac_crc_error : std_logic;
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signal rx_mac_header_rcv : std_logic;
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signal tx_mac_data : byte;
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signal tx_mac_data_en : std_logic;
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signal tx_mac_data_ack : std_logic;
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signal rx_header : mac_header_fields;
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signal tx_header : mac_header_fields;
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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constant TEST_BENCH_LOOPBACK : boolean := true;
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@ -64,20 +56,12 @@ begin
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_header => rx_header,
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rx_mac_header_rcv => rx_mac_header_rcv,
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rx_mac_data => rx_mac_data,
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rx_mac_valid => rx_mac_valid,
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rx_mac_crc_ok => rx_mac_crc_ok,
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rx_mac_crc_error => rx_mac_crc_error,
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tx_header => tx_header,
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tx_mac_data => tx_mac_data,
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tx_mac_data_en => tx_mac_data_en,
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tx_mac_data_ack => tx_mac_data_ack
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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mac_out => mac_out,
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mac_in => mac_in
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);
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clock_driver : process
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@ -147,34 +131,34 @@ begin
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if phy_out.rx_data_valid then
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report "[PHY] RX byte: " & to_hstring(phy_out.rx_data);
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end if;
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if rx_mac_valid then
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report "[MAC] RX byte: " & to_hstring(rx_mac_data);
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if mac_out.rx_mac_valid then
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report "[MAC] RX byte: " & to_hstring(mac_out.rx_mac_data);
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end if;
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if rx_mac_crc_ok then
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if mac_out.rx_mac_crc_ok then
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report "[MAC] RX CRC OK";
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end if;
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if rx_mac_crc_error then
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if mac_out.rx_mac_crc_error then
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report "[MAC] RX CRC error";
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end if;
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end process receiver;
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mac_tx : process is
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begin
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tx_mac_data <= x"11";
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tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
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tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
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tx_header.mac_ethertype <= (x"01", x"00");
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tx_mac_data_en <= '0';
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mac_in.tx_mac_data <= x"11";
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mac_in.tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
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mac_in.tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
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mac_in.tx_header.mac_ethertype <= (x"01", x"00");
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mac_in.tx_mac_data_en <= '0';
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wait until rst = '0';
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wait for 100 ns;
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tx_mac_data_en <= '1';
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wait until rising_edge(tx_mac_data_ack);
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wait until rising_edge(tx_mac_data_ack);
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wait until rising_edge(tx_mac_data_ack);
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mac_in.tx_mac_data_en <= '1';
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wait until rising_edge(mac_out.tx_mac_data_ack);
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wait until rising_edge(mac_out.tx_mac_data_ack);
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wait until rising_edge(mac_out.tx_mac_data_ack);
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wait until rising_edge(clk);
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tx_mac_data_en <= '0';
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mac_in.tx_mac_data_en <= '0';
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wait;
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end process mac_tx;
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@ -18,25 +18,16 @@ use work.trashernet_pkg.all;
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entity trashernet_mac is
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- PHY signals
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phy_out : in phy_out_t; -- PHY application IF (out of PHY)
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phy_in : out phy_in_t; -- PHY application IF (into PHY)
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phy_out : in phy_out_t; -- PHY application IF (out of PHY)
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phy_in : out phy_in_t; -- PHY application IF (into PHY)
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-- MAC signals
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rx_header : out mac_header_fields; -- RX MAC Header Data
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rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid
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rx_mac_data : out byte; -- Ethernet data (after Ethertype)
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rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid
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rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
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rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid
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tx_header : in mac_header_fields; -- TX MAC Header Data
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tx_mac_data : in byte; -- Payload
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tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame
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tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word.
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-- MAC application IF
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mac_out : out mac_out_t; -- MAC application IF (out of MAC)
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mac_in : in mac_in_t -- MAC application IF (into MAC)
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);
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end entity trashernet_mac;
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@ -47,7 +38,7 @@ begin
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rx : block
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type state_t is (HEAD, PAYLOAD);
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constant HEAD_LENGTH : integer := rx_header.mac_destination'length + rx_header.mac_source'length + rx_header.mac_ethertype'length;
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constant HEAD_LENGTH : integer := mac_out.rx_header.mac_destination'length + mac_out.rx_header.mac_source'length + mac_out.rx_header.mac_ethertype'length;
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constant CRC_LENGTH : integer := 4;
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signal state : state_t;
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signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
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@ -81,28 +72,28 @@ begin
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main : process(clk, rst) is
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begin
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if rst then
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byte_count <= 0;
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rx_mac_valid <= '0';
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rx_mac_crc_error <= '0';
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rx_mac_crc_ok <= '0';
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rx_mac_header_rcv <= '0';
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crc_clear <= '0';
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byte_count <= 0;
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mac_out.rx_mac_valid <= '0';
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mac_out.rx_mac_crc_error <= '0';
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mac_out.rx_mac_crc_ok <= '0';
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mac_out.rx_mac_header_rcv <= '0';
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crc_clear <= '0';
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elsif rising_edge(clk) then
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rx_mac_valid <= '0';
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rx_mac_crc_error <= '0';
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rx_mac_crc_ok <= '0';
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rx_mac_header_rcv <= '0';
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crc_clear <= '0';
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mac_out.rx_mac_valid <= '0';
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mac_out.rx_mac_crc_error <= '0';
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mac_out.rx_mac_crc_ok <= '0';
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mac_out.rx_mac_header_rcv <= '0';
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crc_clear <= '0';
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case state is
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when HEAD =>
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if phy_out.rx_data_valid then
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sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & phy_out.rx_data;
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if byte_count = (HEAD_LENGTH - 1) then
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state <= PAYLOAD;
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byte_count <= 0;
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rx_mac_header_rcv <= '1';
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state <= PAYLOAD;
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byte_count <= 0;
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mac_out.rx_mac_header_rcv <= '1';
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end if;
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if (byte_count /= BYTE_COUNT_MAX) then
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@ -113,17 +104,17 @@ begin
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if phy_out.rx_data_valid then
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sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
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if byte_count = CRC_LENGTH then
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rx_mac_valid <= '1';
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mac_out.rx_mac_valid <= '1';
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else
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byte_count <= byte_count + 1;
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end if;
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end if;
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if not phy_out.rx_active then
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rx_mac_crc_ok <= crc_ok;
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rx_mac_crc_error <= not crc_ok;
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mac_out.rx_mac_crc_ok <= crc_ok;
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mac_out.rx_mac_crc_error <= not crc_ok;
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end if;
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if phy_out.rx_error then
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rx_mac_crc_error <= '1';
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mac_out.rx_mac_crc_error <= '1';
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end if;
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end case;
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@ -135,10 +126,10 @@ begin
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end if;
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end process main;
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rx_header.mac_destination <= sr_head(0 to 5);
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rx_header.mac_source <= sr_head(6 to 11);
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rx_header.mac_ethertype <= sr_head(12 to 13);
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rx_mac_data <= sr_payload(0);
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mac_out.rx_header.mac_destination <= sr_head(0 to 5);
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mac_out.rx_header.mac_source <= sr_head(6 to 11);
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mac_out.rx_header.mac_ethertype <= sr_head(12 to 13);
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mac_out.rx_mac_data <= sr_payload(0);
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end block rx;
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@ -146,7 +137,7 @@ begin
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type tx_state_t is (IDLE, HEADER, DATA, TXCRC);
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signal tx_state : tx_state_t;
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signal sr : byte_vector(0 to tx_header.mac_destination'length + tx_header.mac_source'length + tx_header.mac_ethertype'length - 1);
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signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1);
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constant BIT_CNT_MAX : integer := sr'high;
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signal byte_cnt : integer range 0 to BIT_CNT_MAX;
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@ -173,11 +164,11 @@ begin
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tx_main : process(clk, rst) is
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begin
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if rst then
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tx_mac_data_ack <= '0';
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mac_out.tx_mac_data_ack <= '0';
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elsif rising_edge(clk) then
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tx_mac_data_ack <= '0';
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crc_valid <= '0';
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mac_out.tx_mac_data_ack <= '0';
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crc_valid <= '0';
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if phy_out.tx_data_ack then
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sr <= sr(sr'low + 1 to sr'high) & x"00";
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@ -188,7 +179,7 @@ begin
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end if;
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case tx_state is
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when IDLE =>
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if not phy_out.tx_active and tx_mac_data_en then
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if not phy_out.tx_active and mac_in.tx_mac_data_en then
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sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
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byte_cnt <= 7;
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tx_state <= HEADER;
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@ -196,7 +187,7 @@ begin
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when HEADER =>
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if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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sr <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype;
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sr <= mac_in.tx_header.mac_destination & mac_in.tx_header.mac_source & mac_in.tx_header.mac_ethertype;
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crc_valid <= '1';
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byte_cnt <= BIT_CNT_MAX;
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tx_state <= DATA;
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@ -204,9 +195,9 @@ begin
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when DATA =>
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if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
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if tx_mac_data_en then
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sr(0) <= tx_mac_data;
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tx_mac_data_ack <= '1';
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if mac_in.tx_mac_data_en then
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sr(0) <= mac_in.tx_mac_data;
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mac_out.tx_mac_data_ack <= '1';
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else
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sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24));
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byte_cnt <= 4 - 1;
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@ -12,10 +12,12 @@ library ieee;
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use ieee.std_logic_1164.all;
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package trashernet_pkg is
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-- General types
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subtype byte is std_logic_vector(7 downto 0);
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type byte_vector is array (natural range <>) of byte;
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-- MAC specific types
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subtype mac_addr_t is byte_vector(0 to 5);
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subtype ip_addr_t is byte_vector(0 to 3);
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subtype ethertype_t is byte_vector(0 to 1);
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type mac_header_fields is record
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@ -24,6 +26,9 @@ package trashernet_pkg is
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mac_ethertype : ethertype_t; -- Ethertype or length
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end record mac_header_fields;
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-- IP specific types
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subtype ip_addr_t is byte_vector(0 to 3);
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-- PHY interface
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type phy_in_t is record
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tx_data : byte; -- TX Data
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@ -40,6 +45,25 @@ package trashernet_pkg is
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carrier_detect : std_logic; -- Carrier detected
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rx_error : std_logic; -- Receive error
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end record phy_out_t;
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-- MAC interface
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type mac_in_t is record
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tx_header : mac_header_fields; -- TX MAC Header Data
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tx_mac_data : byte; -- Payload
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tx_mac_data_en : std_logic; -- Start (and keep) transmitting a frame
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end record mac_in_t;
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type mac_out_t is record
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rx_header : mac_header_fields; -- RX MAC Header Data
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rx_mac_header_rcv : std_logic; -- `rx_mac` header have been received and are valid
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rx_mac_data : byte; -- Ethernet data (after Ethertype)
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rx_mac_valid : std_logic; -- `rx_mac` values (headers + data) are valid
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tx_mac_data_ack : std_logic; -- The byte on `tx_mac_data` has been latched. Update to next word.
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rx_mac_crc_ok : std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
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rx_mac_crc_error : std_logic; -- End of packet, CRC invalid
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end record mac_out_t;
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end package trashernet_pkg;
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package body trashernet_pkg is
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