Markus Koch 7a0da0f91d eth+ipv4prot: Fix protocol arbitration for real
The problem arises in the following scenario.

There are two sources: HIGH-prio and LOW-prio. Current selection
(from last transaction) is LOW-prio. This one completes.

Next, both request at the same time. Data and tx_en from LOW-prio is
latched -> first word is taken from there. Now, arbitration does its
job and switches to high prio. All acks and data go here.

Result: First byte is from LOW-prio source, rest is from HIGH-prio.

This commit fixes this behavior by resetting the selected channel to
the highest priority one, preventing the switch from pulling it away
from the selected one as the high priority is the one that will get
selected by the switching logic anyways.

Fixes #13.
2025-09-02 14:11:21 +02:00
2025-09-02 12:00:26 +02:00
2022-04-18 10:04:24 +02:00
2025-09-02 09:45:53 +02:00
2022-01-16 17:46:01 +01:00

Trashernet

Trashernet Logo

Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:

  • Layer 1, Physical: trashernet_phy
  • Layer 2, Data link: trashernet_mac, trashernet_eth, trashernet_arp
  • Layer 3, Network: trashernet_ipv4, trashernet_ipv4prot, trashernet_icmp

When writing it, the following were the main design philosophies:

  1. Standards are nice and all, but this, it just needs to work.
  2. Hardware is expensive, LOC are not. So let's do everything we can inside the FPGA.
  3. If there's a feature that feels optional even though it isn't, it is. See 1. if in doubt.

IMPORTANT: This code (and HW suggestions) violate the Ethernet standard in many ways. Do not use in proper (especially commercial) products.

Hardware

Circuit Diagram

  • RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
  • TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)

Notes:

  • The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
  • On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D

Stats

Sythesized for a Lattice LFXP2-5E FPGA using LSE / Diamond v3.12:

Configuration Slices LUT4 Registers
trashernet_phy 115 188 91

License

This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.

The Trashernet logo uses graphics from svgrepo.com, which are released under the Creative Commons CC0 license, granting the right to freely adapt and use them in any context. Thank you for making these available:

The font used in the logo, "White Rabbit" by Matthew Welch, is also released on a free-to-use basis. Thank you!

Description
Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers, including physical!
Readme 546 KiB
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VHDL 96.7%
Python 2.8%
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