Add RMII PHY
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@ -4,7 +4,7 @@
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Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:
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* Layer 1, Physical: `trashernet_phy`
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* Layer 1, Physical: `trashernet_phy`, (`trashernet_rmii`)
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* Layer 2, Data link: `trashernet_mac`, `trashernet_eth`, `trashernet_arp`
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* Layer 3, Network: `trashernet_ipv4`, `trashernet_ipv4prot`, `trashernet_icmp`
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@ -16,6 +16,8 @@ When writing it, the following were the main design philosophies:
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**IMPORTANT:** This code (and HW suggestions) violate the Ethernet standard in many ways. Do not use in proper (especially commercial) products.
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Note: The `trashernet_rmii` component uses a standard RMII Ethernet PHY instead of the hardware suggestions below. If you are looking for the true Trashernet experience, choose the `trashernet_phy` instead.
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## Hardware
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218
bench/bench_trashernet_rmii.vhd
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218
bench/bench_trashernet_rmii.vhd
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@ -0,0 +1,218 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- bench_trashernet_mac.vhd : Stimulus-only test bench for the MAC+PHY parts
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-- Tests TX path through the RX path. Not great, but whatever.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.bench_pkg.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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entity bench_trashernet_rmii is
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generic(
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runner_cfg : string
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);
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end entity bench_trashernet_rmii;
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architecture bench of bench_trashernet_rmii is
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signal clk : std_logic;
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signal rst : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rmii_ref_clk : std_logic;
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signal rmii_crs_dv : std_logic;
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signal rmii_rxd : std_logic_vector(1 downto 0);
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signal rmii_tx_en : std_logic;
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signal rmii_txd : std_logic_vector(1 downto 0);
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signal rmii_tx_start : std_logic := '0';
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signal trashernet_tx_start : std_logic := '0';
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begin
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trashernet_rmii_inst : entity trashernet.trashernet_rmii
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generic map(
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SYSCLK_IS_REFCLK => false
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)
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rmii_ref_clk => rmii_ref_clk,
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rmii_crs_dv => rmii_crs_dv,
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rmii_rxd => rmii_rxd,
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rmii_tx_en => rmii_tx_en,
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rmii_txd => rmii_txd
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);
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clockDriver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clockDriver;
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test : process is
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begin
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rst <= '1';
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test_runner_setup(runner, runner_cfg);
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wait for 10 ns;
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rst <= '0';
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wait for 10 ns;
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while test_suite loop
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if run("rx") then
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rmii_tx_start <= not rmii_tx_start;
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wait until phy_out.rx_active = '1' for 1 ms;
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assert phy_out.rx_active'event report "Timeout for reception to start";
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wait until phy_out.rx_active = '0' for 1 ms;
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assert phy_out.rx_active'event report "Timeout for reception to end";
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wait for 1 us;
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elsif run("tx") then
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trashernet_tx_start <= not trashernet_tx_start;
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wait until phy_out.tx_active = '1' for 1 ms;
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assert phy_out.tx_active'event report "Timeout for transmission to start";
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wait until phy_out.tx_active = '0' for 1 ms;
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assert phy_out.tx_active'event report "Timeout for transmission to stop";
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wait until phy_out.tx_active = '1' for 1 ms;
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assert phy_out.tx_active'event report "Timeout for transmission to start";
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wait until phy_out.tx_active = '0' for 1 ms;
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assert phy_out.tx_active'event report "Timeout for transmission to stop";
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end if;
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end loop;
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wait for 1 ns;
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test_runner_cleanup(runner);
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end process test;
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phy_rx : process(clk) is
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begin
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if rising_edge(clk) then
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if phy_out.rx_data_valid = '1' then
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report "RX data: " & to_hstring(phy_out.rx_data);
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end if;
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end if;
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end process phy_rx;
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rmiirefclk : process
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constant period : time := 20 ns;
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begin
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rmii_ref_clk <= '0';
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wait for period / 2;
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rmii_ref_clk <= '1';
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wait for period / 2;
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end process rmiirefclk;
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rmii_tx_gen : process is
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procedure send_frame(data : byte_vector) is
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variable sr : byte;
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begin
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wait until rising_edge(rmii_ref_clk);
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rmii_rxd <= "01";
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wait for 2.5 ns;
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rmii_crs_dv <= '1';
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for i in 0 to 10 loop
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wait until rmii_ref_clk;
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end loop;
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rmii_rxd <= "11";
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wait until rmii_ref_clk;
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for i in data'range loop
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sr := data(i);
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for j in 0 to 3 loop
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rmii_rxd <= sr(1 downto 0);
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wait until rising_edge(rmii_ref_clk);
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sr := "XX" & sr(sr'high downto 2);
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end loop;
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end loop;
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rmii_crs_dv <= '0';
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wait for 1 us; -- IPG
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end procedure send_frame;
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begin
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rmii_crs_dv <= '0';
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rmii_rxd <= (others => '0');
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wait on rmii_tx_start;
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send_frame(byte_vector'(x"c6", x"b8", x"c1", x"db", x"b1", x"1d", x"00", x"ff", x"ff", x"11", x"22", x"33", x"08", x"00", x"45", x"00", x"00", x"29", x"00", x"00", x"00", x"00", x"40", x"11", x"f5", x"70", x"c0", x"a8", x"02", x"02", x"c0", x"a8", x"02", x"01", x"ab", x"cd", x"00", x"ff", x"00", x"15", x"00", x"00", x"48", x"65", x"6c", x"6c", x"6f", x"20", x"57", x"6f", x"72", x"6c", x"64", x"21", x"0a", x"00", x"00", x"00", x"00", x"00", x"64", x"90", x"a9", x"ea"));
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wait;
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end process rmii_tx_gen;
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trashernet_tx_gen : process is
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procedure send_frame(data : byte_vector) is
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begin
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for i in data'range loop
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phy_in.tx_data_en <= '1';
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phy_in.tx_data <= data(i);
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wait until rising_edge(clk);
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while not phy_out.tx_data_ack loop
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wait until rising_edge(clk);
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end loop;
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end loop;
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phy_in.tx_data_en <= '0';
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wait until rising_edge(clk);
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end procedure send_frame;
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begin
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phy_in.tx_data_en <= '0';
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wait on trashernet_tx_start;
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wait until rising_edge(clk);
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send_frame(byte_vector'(x"c6", x"b8", x"c1", x"db", x"b1", x"1d", x"00", x"ff", x"ff", x"11", x"22", x"33", x"08", x"00", x"45", x"00", x"00", x"29", x"00", x"00", x"00", x"00", x"40", x"11", x"f5", x"70", x"c0", x"a8", x"02", x"02", x"c0", x"a8", x"02", x"01", x"ab", x"cd", x"00", x"ff", x"00", x"15", x"00", x"00", x"48", x"65", x"6c", x"6c", x"6f", x"20", x"57", x"6f", x"72", x"6c", x"64", x"21", x"0a", x"00", x"00", x"00", x"00", x"00", x"64", x"90", x"a9", x"ea"));
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-- Currently, there's a bug in the CDC preventing single-cycle deassertions from deasserting the transmit enable
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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send_frame(byte_vector'(x"c6", x"b8", x"c1", x"db", x"b1", x"1d", x"00", x"ff", x"ff", x"11", x"22", x"33", x"08", x"00", x"45", x"00", x"00", x"29", x"00", x"00", x"00", x"00", x"40", x"11", x"f5", x"70", x"c0", x"a8", x"02", x"02", x"c0", x"a8", x"02", x"01", x"ab", x"cd", x"00", x"ff", x"00", x"15", x"00", x"00", x"48", x"65", x"6c", x"6c", x"6f", x"20", x"57", x"6f", x"72", x"6c", x"64", x"21", x"0a", x"00", x"00", x"00", x"00", x"00", x"64", x"90", x"a9", x"ea"));
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end process trashernet_tx_gen;
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rmii_receiver : process(rmii_ref_clk) is
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variable sr : byte;
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variable cnt : integer range 0 to 3;
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variable active : boolean := false;
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begin
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if rising_edge(rmii_ref_clk) then
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if rmii_tx_en then
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if not active then
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report "RMII RX start";
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end if;
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sr := rmii_txd & sr(sr'high downto 2);
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if cnt = 3 then
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cnt := 0;
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report "RMII RX: " & to_hstring(sr);
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else
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cnt := cnt + 1;
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end if;
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active := true;
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else
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if active then
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report "RMII RX stop";
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end if;
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cnt := 0;
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active := false;
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end if;
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end if;
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end process rmii_receiver;
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end architecture bench;
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trashernet/trashernet_rmii.vhd
Normal file
300
trashernet/trashernet_rmii.vhd
Normal file
@ -0,0 +1,300 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- trashernet_rmii.vhd : Ethernet OSI Layer 1, Physical
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-- Implements interface to an RMII PHY.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.trashernet_pkg.all;
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entity trashernet_rmii is
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generic(
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SYSCLK_IS_REFCLK : boolean := false -- Do not generate synchronizers between the RMII and system clock domains
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);
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port(
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-- Global
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clk : in std_logic; -- Global clock (must not be slower than rmii_ref_clk)
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rst : in std_logic; -- Asynchronous reset
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-- PHY application interface
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phy_out : out phy_out_t; -- PHY application IF (out)
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phy_in : in phy_in_t; -- PHY application IF (in)
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-- RMII physical signals
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rmii_ref_clk : in std_logic; -- Synchronous clock reference for receive, transmit and control interface
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rmii_crs_dv : in std_logic; -- Carrier Sense/Receive Data Valid
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rmii_rxd : in std_logic_vector(1 downto 0); -- Receive Data
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rmii_tx_en : out std_logic; -- Transmit Enable
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rmii_txd : out std_logic_vector(1 downto 0) -- Transmit Data
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);
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end entity trashernet_rmii;
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architecture rtl of trashernet_rmii is
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signal rmii_rst : std_logic;
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signal rmii_crs_dv_sync : std_logic;
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begin
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synchronizer_inst : entity work.synchronizer
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generic map(
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SIZE => 2
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)
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port map(
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clk => clk,
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rst => rst,
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data_in => rmii_crs_dv,
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data_out => rmii_crs_dv_sync
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);
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rmii_reset_gen : if SYSCLK_IS_REFCLK generate
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rmii_rst <= rst;
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else generate
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rmii_reset_gen_p : process(rmii_ref_clk, rst) is
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begin
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if rst then
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rmii_rst <= '1';
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elsif rising_edge(rmii_ref_clk) then
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rmii_rst <= '0';
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end if;
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end process rmii_reset_gen_p;
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end generate rmii_reset_gen;
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receive : block
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type state_t is (IDLE, DATA);
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signal state : state_t;
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signal sr : byte;
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signal dibit_cnt : integer range 0 to 3;
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signal temp_rx_data : byte;
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signal temp_rx_active : std_logic;
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signal temp_rx_data_valid : std_logic;
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begin
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rxp : process(rmii_rst, rmii_ref_clk) is
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begin
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if rmii_rst then
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state <= IDLE;
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elsif rising_edge(rmii_ref_clk) then
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-- Shift in data bytes
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sr <= rmii_rxd & sr(sr'high downto 2);
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if dibit_cnt = 3 then
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dibit_cnt <= 0;
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else
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dibit_cnt <= dibit_cnt + 1;
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end if;
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-- Sync header
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case state is
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when IDLE =>
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if sr = x"D5" then -- Sync header
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state <= DATA;
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dibit_cnt <= 1;
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end if;
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when DATA =>
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null;
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end case;
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-- Stop receiving whenever CRSDV disappears
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if rmii_crs_dv_sync = '0' then
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state <= IDLE;
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end if;
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end if;
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end process rxp;
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temp_rx_data <= sr;
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temp_rx_active <= '1' when (state = DATA) else '0'; -- TODO: We might want to delay this by one cycle
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temp_rx_data_valid <= '1' when (state = DATA) and (dibit_cnt = 0) else '0';
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phy_out.rx_error <= '0'; -- We don't implement RXER
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phy_out.carrier_detect <= '1'; -- TODO: Not yet implemented.
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cdc_or_register : if SYSCLK_IS_REFCLK generate
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register_out : process(rmii_rst, rmii_ref_clk) is
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begin
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if rmii_rst then
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phy_out.rx_data <= (others => '0');
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phy_out.rx_active <= '0';
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phy_out.rx_data_valid <= '0';
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elsif rising_edge(rmii_ref_clk) then
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phy_out.rx_data <= temp_rx_data;
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phy_out.rx_active <= temp_rx_active;
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phy_out.rx_data_valid <= temp_rx_data_valid;
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end if;
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end process register_out;
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else generate
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-- CDC
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synchronizer_inst : entity work.synchronizer
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generic map(
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SIZE => 2
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)
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port map(
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clk => clk,
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rst => rst,
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data_in => temp_rx_active,
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data_out => phy_out.rx_active
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);
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cdc_strobe_inst : entity work.cdc_strobe
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generic map(
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SYNCHRONIZERS => 2
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)
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port map(
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a_clk => rmii_ref_clk,
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a_rst => rmii_rst,
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a_in => temp_rx_data_valid,
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b_clk => clk,
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b_rst => rst,
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b_out => phy_out.rx_data_valid
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);
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-- Not a synchronizer, just a byte latch in the rmii_ref_clk domain
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rx_data_reg : process(rmii_ref_clk) is
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begin
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if rising_edge(rmii_ref_clk) then
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if temp_rx_data_valid then
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phy_out.rx_data <= temp_rx_data; -- TODO: We are assuming that the system clock domains runs at least x times faster than the PHY clock domain
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end if;
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end if;
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end process rx_data_reg;
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end generate cdc_or_register;
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end block receive;
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transmitter : block
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constant SYNC_HEADER_SIZE_BYTES : natural := 8 - 1; -- Sync header 0x55 bytes ()
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constant IPG_SIZE_BYTES : natural := 96 / 8;
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signal temp_tx_data : byte;
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signal temp_tx_data_en : std_logic;
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signal temp_tx_data_ack : std_logic;
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type state_t is (IDLE, HEADER, DATA, IPG);
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signal state : state_t;
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signal sr : byte;
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signal dibit_cnt : integer range 0 to 3;
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signal byte_cnt : integer range 0 to maximum(SYNC_HEADER_SIZE_BYTES, IPG_SIZE_BYTES) - 1;
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signal byte_done : std_logic;
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signal block_done : std_logic;
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begin
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cdc_or_register : if SYSCLK_IS_REFCLK generate
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temp_tx_data_en <= phy_in.tx_data_en;
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temp_tx_data <= phy_in.tx_data;
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|
||||
-- -----------------------------------------------------------------
|
||||
|
||||
phy_out_reg : process(rst, clk) is
|
||||
begin
|
||||
if rst then
|
||||
phy_out.tx_data_ack <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
phy_out.tx_data_ack <= temp_tx_data_ack;
|
||||
end if;
|
||||
end process phy_out_reg;
|
||||
|
||||
else generate
|
||||
synchronizer_txdv_inst : entity work.synchronizer
|
||||
generic map(
|
||||
SIZE => 2
|
||||
)
|
||||
port map(
|
||||
clk => rmii_ref_clk,
|
||||
rst => rmii_rst,
|
||||
data_in => phy_in.tx_data_en,
|
||||
data_out => temp_tx_data_en
|
||||
);
|
||||
temp_tx_data <= phy_in.tx_data; -- TODO: Again, we are making assumptions about the clock relationship here
|
||||
|
||||
-- -----------------------------------------------------------------
|
||||
|
||||
cdc_strobe_inst : entity work.cdc_strobe
|
||||
generic map(
|
||||
SYNCHRONIZERS => 2
|
||||
)
|
||||
port map(
|
||||
a_clk => rmii_ref_clk,
|
||||
a_rst => rmii_rst,
|
||||
a_in => temp_tx_data_ack,
|
||||
b_clk => clk,
|
||||
b_rst => rst,
|
||||
b_out => phy_out.tx_data_ack
|
||||
);
|
||||
end generate cdc_or_register;
|
||||
|
||||
txp : process(rmii_ref_clk, rmii_rst) is
|
||||
begin
|
||||
if rmii_rst then
|
||||
state <= IDLE;
|
||||
|
||||
elsif rising_edge(rmii_ref_clk) then
|
||||
sr <= "00" & sr(sr'high downto 2);
|
||||
if dibit_cnt = 3 then
|
||||
dibit_cnt <= 0;
|
||||
else
|
||||
dibit_cnt <= dibit_cnt + 1;
|
||||
end if;
|
||||
if byte_done then
|
||||
if byte_cnt > 0 then
|
||||
byte_cnt <= byte_cnt - 1;
|
||||
else
|
||||
end if;
|
||||
end if;
|
||||
|
||||
case state is
|
||||
when IDLE =>
|
||||
sr <= x"55";
|
||||
byte_cnt <= SYNC_HEADER_SIZE_BYTES - 1;
|
||||
dibit_cnt <= 0;
|
||||
if temp_tx_data_en then
|
||||
state <= HEADER;
|
||||
end if;
|
||||
|
||||
when HEADER =>
|
||||
sr <= x"55";
|
||||
if not temp_tx_data_en then
|
||||
state <= IDLE;
|
||||
elsif block_done then
|
||||
sr <= x"D5";
|
||||
state <= DATA;
|
||||
end if;
|
||||
|
||||
when DATA =>
|
||||
if byte_done then
|
||||
if temp_tx_data_en then
|
||||
sr <= temp_tx_data;
|
||||
else
|
||||
state <= IPG;
|
||||
byte_cnt <= IPG_SIZE_BYTES - 1;
|
||||
end if;
|
||||
end if;
|
||||
when IPG =>
|
||||
if block_done then
|
||||
state <= IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process txp;
|
||||
byte_done <= '1' when dibit_cnt = 3 else '0';
|
||||
block_done <= '1' when (byte_cnt = 0) and (byte_done = '1') else '0';
|
||||
temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0';
|
||||
phy_out.tx_active <= '1' when (state = HEADER) or (state = DATA) else '0';
|
||||
|
||||
rmii_txd <= sr(1 downto 0);
|
||||
rmii_tx_en <= '1' when (state = HEADER) or (state = DATA) else '0';
|
||||
end block transmitter;
|
||||
end architecture rtl;
|
||||
|
Loading…
x
Reference in New Issue
Block a user