Reformat code using latest version of Sigasi
This commit is contained in:
parent
154604aacd
commit
f67e8d8b37
@ -1,35 +1,10 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
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<Mappings Location="bench" Library="bench"/>
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<Mappings Location="cocotb" Library="cocotb"/>
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<Mappings Location="design" Library="design"/>
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<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
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<Mappings Location="Common Libraries/IEEE Synopsys" Library="ieee"/>
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<Mappings Location="" Library="not mapped"/>
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<Mappings Location="Common Libraries" Library="not mapped"/>
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<Mappings Location="Common Libraries/vunit" Library="not mapped"/>
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<Mappings Location="cocotb/__pycache__" Library="not mapped"/>
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<Mappings Location="cocotb/sim_build" Library="not mapped"/>
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<Mappings Location="Common Libraries/STD" Library="std"/>
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<Mappings Location="trashernet" Library="trashernet"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/IP_complete_nomac.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/IPv4.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/IPv4_RX.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/IPv4_TX.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/UDP_Complete_nomac.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/UDP_RX.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/UDP_TX.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp_REQ.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp_RX.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp_STORE_br.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp_SYNC.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp_TX.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arp_types.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/arpv2.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/axi.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/ipv4_types.vhd" Library="udpip"/>
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<Mappings Location="udp_ip_stack/rtl/vhdl/tx_arbitrator.vhd" Library="udpip"/>
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<Mappings Location="Common Libraries/vunit/vunit/vhdl" Library="vunit_lib"/>
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<Mappings Location="Common Libraries/src" Library="xp2"/>
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</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>
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27
.project
27
.project
@ -5,16 +5,6 @@
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.ui.externaltools.ExternalToolBuilder</name>
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<triggers>full,incremental,</triggers>
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<arguments>
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<dictionary>
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<key>LaunchConfigHandle</key>
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<value><project>/.externalToolBuilders/com.sigasi.hdt.toolchains.vunit.builder.launch</value>
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</dictionary>
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</arguments>
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</buildCommand>
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<buildCommand>
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<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
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<arguments>
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@ -22,9 +12,9 @@
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</buildCommand>
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</buildSpec>
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<natures>
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<nature>com.sigasi.hdt.verilog.ui.verilogNature</nature>
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<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
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<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
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<nature>com.sigasi.hdt.toolchains.vunit.nature</nature>
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</natures>
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<linkedResources>
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<link>
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@ -32,11 +22,6 @@
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
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<type>1</type>
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<locationURI>sigasiresource:/vhdl/readme.txt</locationURI>
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</link>
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<link>
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<name>Common Libraries/IEEE</name>
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<type>2</type>
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@ -52,15 +37,5 @@
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/2008/STD</locationURI>
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</link>
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<link>
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<name>Common Libraries/src</name>
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<type>2</type>
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<location>/usr/local/diamond/3.12/cae_library/simulation/vhdl/xp2/src</location>
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</link>
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<link>
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<name>Common Libraries/vunit</name>
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<type>2</type>
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<locationURI>PARENT-1-PROJECT_LOC/vunit</locationURI>
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</link>
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</linkedResources>
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</projectDescription>
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@ -1,2 +0,0 @@
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VUnitScriptLocation=vunit/run.py
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eclipse.preferences.version=1
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2
.settings/com.sigasi.hdt.verilog.linting.prefs
Normal file
2
.settings/com.sigasi.hdt.verilog.linting.prefs
Normal file
@ -0,0 +1,2 @@
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eclipse.preferences.version=1
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isEnabled=true
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1
.settings/com.sigasi.hdt.verilog.version.prefs
Normal file
1
.settings/com.sigasi.hdt.verilog.version.prefs
Normal file
@ -0,0 +1 @@
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<project>=sv2012
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2
.settings/com.sigasi.hdt.vhdl.linting.prefs
Normal file
2
.settings/com.sigasi.hdt.vhdl.linting.prefs
Normal file
@ -0,0 +1,2 @@
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eclipse.preferences.version=1
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isEnabled=true
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@ -1,5 +1,5 @@
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eclipse.preferences.version=1
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encoding//Common\ Libraries/IEEE=utf-8
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encoding//Common\ Libraries/IEEE\ Synopsys=utf-8
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encoding//Common\ Libraries/STD=utf-8
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encoding/Common\ Libraries=utf-8
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encoding//Common\ Libraries/IEEE=UTF-8
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encoding//Common\ Libraries/IEEE\ Synopsys=UTF-8
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encoding//Common\ Libraries/STD=UTF-8
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encoding//Common\ Libraries=UTF-8
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@ -19,12 +19,12 @@ end entity bench_crc;
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architecture bench of bench_crc is
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constant POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7";
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signal clk : std_logic;
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signal rst : std_logic;
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signal data : std_logic_vector(7 downto 0);
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signal data_valid : std_logic;
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signal crc_clear : std_logic;
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signal crc_out : std_logic_vector(POLYNOMIAL'range);
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signal clk : std_logic;
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signal rst : std_logic;
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signal data : std_logic_vector(7 downto 0);
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signal data_valid : std_logic;
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signal crc_clear : std_logic;
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signal crc_out : std_logic_vector(POLYNOMIAL'range);
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begin
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crc_inst : entity trashernet.crc
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generic map(
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@ -30,7 +30,7 @@ package body bench_pkg is
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wait for 50 ns;
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end loop;
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end loop;
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wait for 16 us; -- IPG
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wait for 16 us; -- IPG
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report "Frame TX complete";
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end procedure send_data;
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end package body bench_pkg;
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@ -22,15 +22,14 @@ entity bench_trashernet_phy is
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end entity bench_trashernet_phy;
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architecture bench of bench_trashernet_phy is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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begin
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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@ -39,14 +38,14 @@ begin
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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clock_driver : process
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@ -29,8 +29,8 @@ end entity ledcon;
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architecture RTL of ledcon is
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constant MS_CNT_MAX : integer := integer(round(real(F_CLK) * (1.0 * 10.0 ** (-3))));
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signal ms_cnt : integer range 0 to MS_CNT_MAX;
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signal ms_tick : std_logic;
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signal ms_cnt : integer range 0 to MS_CNT_MAX;
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signal ms_tick : std_logic;
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begin
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mstimer : process(clk, rst) is
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begin
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@ -50,7 +50,7 @@ begin
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ledblock : block
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constant LED_CNT_MAX : integer := 50; -- on time, in ms
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constant LED_CNT_MIN : integer := -50; -- off time, in ms
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signal led_cnt : integer range LED_CNT_MIN to LED_CNT_MAX;
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signal led_cnt : integer range LED_CNT_MIN to LED_CNT_MAX;
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begin
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ledgen : if BLINK(i) generate
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ledproc : process(clk, rst) is
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@ -57,13 +57,13 @@ architecture mac of top_hwitl is
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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type status_t is (IDLE, TX);
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signal state : status_t;
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type status_t is (IDLE, TX);
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signal state : status_t;
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constant BYTE_CNT_MAX : integer := 100;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1;
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signal tmo : integer range 0 to TMO_MAX;
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signal tmo : integer range 0 to TMO_MAX;
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begin
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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@ -206,10 +206,10 @@ architecture eth of top_hwitl is
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PROT_ARP => ETHERNET_II_PROTOCOL_ARP,
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PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4
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);
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signal ethernet_i_out : ethernet_i_out_t;
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signal ethernet_i_in : ethernet_i_in_t;
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signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_i_out : ethernet_i_out_t;
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signal ethernet_i_in : ethernet_i_in_t;
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signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
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signal arp_out : arp_out_t;
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signal arp_in : arp_in_t;
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@ -217,14 +217,14 @@ architecture eth of top_hwitl is
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signal ipv4_out : ipv4_out_t;
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signal ipv4_in : ipv4_in_t;
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constant IPROT_ICMP : integer := 0;
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constant IPROT_UDP : integer := 1;
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constant IPV4_PROTOCOLS : ipv4_protocol_vector := (
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constant IPROT_ICMP : integer := 0;
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constant IPROT_UDP : integer := 1;
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constant IPV4_PROTOCOLS : ipv4_protocol_vector := (
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IPROT_ICMP => IPV4_PROTOCOL_ICMP,
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IPROT_UDP => IPV4_PROTOCOL_UDP
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);
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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signal udp_out : udp_out_t;
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signal udp_in : udp_in_t;
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@ -68,16 +68,16 @@ architecture rtl of top_mac_test is
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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type status_t is (IDLE, TX);
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signal state : status_t;
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type status_t is (IDLE, TX);
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signal state : status_t;
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constant BYTE_CNT_MAX : integer := 100;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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signal button_n_sync : std_logic_vector(button_n'range);
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signal button : std_logic_vector(button_n'range);
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constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1;
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signal tmo : integer range 0 to TMO_MAX;
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signal tmo : integer range 0 to TMO_MAX;
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begin
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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@ -190,7 +190,7 @@ begin
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if mac_out.tx_mac_data_ack then
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if byte_cnt = 1 then
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mac_in.tx_mac_data_en <= '0';
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state <= IDLE;
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state <= IDLE;
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else
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byte_cnt <= byte_cnt - 1;
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end if;
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@ -79,10 +79,10 @@ architecture rtl of top_pingable is
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PROT_ARP => ETHERNET_II_PROTOCOL_ARP,
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PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4
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);
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signal ethernet_i_out : ethernet_i_out_t;
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signal ethernet_i_in : ethernet_i_in_t;
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signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_i_out : ethernet_i_out_t;
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signal ethernet_i_in : ethernet_i_in_t;
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signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
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signal arp_out : arp_out_t;
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signal arp_in : arp_in_t;
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@ -90,12 +90,12 @@ architecture rtl of top_pingable is
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signal ipv4_out : ipv4_out_t;
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signal ipv4_in : ipv4_in_t;
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constant IPROT_ICMP : integer := 0;
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constant IPV4_PROTOCOLS : ipv4_protocol_vector := (
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constant IPROT_ICMP : integer := 0;
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constant IPV4_PROTOCOLS : ipv4_protocol_vector := (
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IPROT_ICMP => IPV4_PROTOCOL_ICMP
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);
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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signal button_n_sync : std_logic_vector(button_n'range);
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signal button : std_logic_vector(button_n'range);
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@ -34,11 +34,11 @@ entity fifo is
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end entity fifo;
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architecture rtl of fifo is
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type memory_t is array (natural range <>) of std_logic_vector(data_in'range);
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signal memory : memory_t(0 to DEPTH - 1);
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type memory_t is array (natural range <>) of std_logic_vector(data_in'range);
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signal memory : memory_t(0 to DEPTH - 1);
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subtype memory_pointer_t is integer range 0 to DEPTH - 1;
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subtype usage_counter_t is integer range 0 to DEPTH;
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subtype usage_counter_t is integer range 0 to DEPTH;
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signal read_pointer : memory_pointer_t;
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signal write_pointer : memory_pointer_t;
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@ -64,8 +64,8 @@ architecture rtl of trashernet_arp is
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begin
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resolver : block
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type resolver_state_t is (IDLE, QUERY_MAC);
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signal state : resolver_state_t;
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type resolver_state_t is (IDLE, QUERY_MAC);
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signal state : resolver_state_t;
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signal query_mac_found : std_logic;
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signal query_timeout : std_logic := '0'; -- TODO: Implement
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@ -146,19 +146,19 @@ begin
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signal sr : byte_vector(0 to BYTECOUNT_ADDRESSES - 1);
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constant SR_HEAD_OFFSET : integer := BYTECOUNT_ADDRESSES - BYTECOUNT_HEAD;
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alias sr_head_htype is sr(SR_HEAD_OFFSET + 0 to SR_HEAD_OFFSET + 1);
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alias sr_head_ptype is sr(SR_HEAD_OFFSET + 2 to SR_HEAD_OFFSET + 3);
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alias sr_head_hlen is sr(SR_HEAD_OFFSET + 4);
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alias sr_head_plen is sr(SR_HEAD_OFFSET + 5);
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alias sr_head_oper is sr(SR_HEAD_OFFSET + 6 to SR_HEAD_OFFSET + 7);
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alias sr_head_htype is sr(SR_HEAD_OFFSET + 0 to SR_HEAD_OFFSET + 1);
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alias sr_head_ptype is sr(SR_HEAD_OFFSET + 2 to SR_HEAD_OFFSET + 3);
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alias sr_head_hlen is sr(SR_HEAD_OFFSET + 4);
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alias sr_head_plen is sr(SR_HEAD_OFFSET + 5);
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alias sr_head_oper is sr(SR_HEAD_OFFSET + 6 to SR_HEAD_OFFSET + 7);
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constant SR_ADDRESSES_OFFSET : integer := -8;
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alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC
|
||||
alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET);
|
||||
alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET);
|
||||
alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET);
|
||||
alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC
|
||||
alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET);
|
||||
|
||||
type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE);
|
||||
type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE);
|
||||
signal state : state_t;
|
||||
signal bytecount : integer range 0 to BYTECOUNT_ADDRESSES;
|
||||
signal shifted : std_logic;
|
||||
@ -240,7 +240,7 @@ begin
|
||||
state <= HEAD;
|
||||
end if;
|
||||
|
||||
when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err)
|
||||
when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err)
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
@ -253,14 +253,14 @@ begin
|
||||
end block rx;
|
||||
|
||||
tx : block
|
||||
signal sr : byte_vector(0 to 27);
|
||||
signal arp_reply_preload : byte_vector(sr'range);
|
||||
signal arp_request_preload : byte_vector(sr'range);
|
||||
constant BYTECOUNT_MAX : integer := sr'length + 1;
|
||||
signal bytecount : integer range 0 to BYTECOUNT_MAX;
|
||||
signal sr : byte_vector(0 to 27);
|
||||
signal arp_reply_preload : byte_vector(sr'range);
|
||||
signal arp_request_preload : byte_vector(sr'range);
|
||||
constant BYTECOUNT_MAX : integer := sr'length + 1;
|
||||
signal bytecount : integer range 0 to BYTECOUNT_MAX;
|
||||
|
||||
type state_t is (IDLE, TRANSMIT);
|
||||
signal state : state_t;
|
||||
type state_t is (IDLE, TRANSMIT);
|
||||
signal state : state_t;
|
||||
begin
|
||||
|
||||
arp_reply_preload <= HTYPE & PTYPE & HLEN & PLEN & OPER_REPLY & -- Header
|
||||
|
@ -46,11 +46,11 @@ architecture rtl of trashernet_eth is
|
||||
signal tx_data_ack_i : std_logic;
|
||||
begin
|
||||
rx : block
|
||||
constant SEL_ETH_I : integer := ethernet_ii_out'low - 1;
|
||||
constant SEL_ETH_NONE : integer := ethernet_ii_out'low - 2;
|
||||
signal sel : integer range SEL_ETH_NONE to ethernet_ii_out'high;
|
||||
signal mac_destination_matches : std_logic;
|
||||
signal rx_mac_header_rcv_delayed : std_logic;
|
||||
constant SEL_ETH_I : integer := ethernet_ii_out'low - 1;
|
||||
constant SEL_ETH_NONE : integer := ethernet_ii_out'low - 2;
|
||||
signal sel : integer range SEL_ETH_NONE to ethernet_ii_out'high;
|
||||
signal mac_destination_matches : std_logic;
|
||||
signal rx_mac_header_rcv_delayed : std_logic;
|
||||
|
||||
begin
|
||||
mac_destination_matches <= '1' when --
|
||||
@ -112,10 +112,10 @@ begin
|
||||
end block rx;
|
||||
|
||||
tx : block
|
||||
type state_t is (IDLE, TXD);
|
||||
signal state : state_t;
|
||||
type state_t is (IDLE, TXD);
|
||||
signal state : state_t;
|
||||
constant SEL_ETH_I : integer := ethernet_ii_out'low - 1;
|
||||
signal sel : integer range SEL_ETH_I to ethernet_ii_in'high;
|
||||
signal sel : integer range SEL_ETH_I to ethernet_ii_in'high;
|
||||
begin
|
||||
arb : process(clk, rst) is
|
||||
begin
|
||||
|
@ -56,13 +56,13 @@ begin
|
||||
);
|
||||
|
||||
rx : block
|
||||
signal sr : byte_vector(0 to 3);
|
||||
alias sr_type is sr(0);
|
||||
alias sr_code is sr(1);
|
||||
alias sr_checksum is sr(2 to 3);
|
||||
signal sr : byte_vector(0 to 3);
|
||||
alias sr_type is sr(0);
|
||||
alias sr_code is sr(1);
|
||||
alias sr_checksum is sr(2 to 3);
|
||||
|
||||
type state_t is (HEADER, DATA, IGNORE);
|
||||
signal state : state_t;
|
||||
type state_t is (HEADER, DATA, IGNORE);
|
||||
signal state : state_t;
|
||||
|
||||
signal byte_count : integer range 0 to sr'length;
|
||||
|
||||
@ -117,8 +117,8 @@ begin
|
||||
signal checksum : unsigned(16 downto 0);
|
||||
signal checksum_ones : unsigned(15 downto 0);
|
||||
|
||||
type state_t is (IDLE, HEADER, PAYLOAD);
|
||||
signal state : state_t;
|
||||
type state_t is (IDLE, HEADER, PAYLOAD);
|
||||
signal state : state_t;
|
||||
|
||||
signal sr : byte_vector(0 to 3);
|
||||
signal byte_count : integer range 0 to sr'subtype'high;
|
||||
|
@ -44,27 +44,27 @@ begin
|
||||
constant BYTECOUNT_HEADER : integer := 20; -- Mandatory header fields
|
||||
|
||||
signal sr : byte_vector(0 to BYTECOUNT_HEADER - 1) := (others => x"00"); -- Init to zero to squelch metavalue warnings
|
||||
alias sr_version is sr(0)(7 downto 4);
|
||||
alias sr_ihl is sr(0)(3 downto 0);
|
||||
alias sr_dscp is sr(1)(7 downto 2);
|
||||
alias sr_ecn is sr(1)(1 downto 0);
|
||||
alias sr_total_length is sr(2 to 3);
|
||||
alias sr_identification is sr(4 to 5);
|
||||
alias sr_flags is sr(6)(7 downto 5);
|
||||
alias sr_version is sr(0)(7 downto 4);
|
||||
alias sr_ihl is sr(0)(3 downto 0);
|
||||
alias sr_dscp is sr(1)(7 downto 2);
|
||||
alias sr_ecn is sr(1)(1 downto 0);
|
||||
alias sr_total_length is sr(2 to 3);
|
||||
alias sr_identification is sr(4 to 5);
|
||||
alias sr_flags is sr(6)(7 downto 5);
|
||||
signal sr_fragment_offset : std_logic_vector(12 downto 0);
|
||||
alias sr_ttl is sr(8);
|
||||
alias sr_protocol is sr(9);
|
||||
alias sr_header_cks is sr(10 to 11);
|
||||
alias sr_source_ip is sr(12 to 15);
|
||||
alias sr_destination_ip is sr(16 to 19);
|
||||
alias sr_ttl is sr(8);
|
||||
alias sr_protocol is sr(9);
|
||||
alias sr_header_cks is sr(10 to 11);
|
||||
alias sr_source_ip is sr(12 to 15);
|
||||
alias sr_destination_ip is sr(16 to 19);
|
||||
|
||||
signal header_ok : std_logic;
|
||||
|
||||
signal bytecount : integer range 0 to 65535;
|
||||
signal block_done : std_logic;
|
||||
|
||||
type state_t is (HEADER, OPT, PAYLOAD, DONE);
|
||||
signal state : state_t;
|
||||
type state_t is (HEADER, OPT, PAYLOAD, DONE);
|
||||
signal state : state_t;
|
||||
begin
|
||||
sr_fragment_offset <= sr(6)(4 downto 0) & sr(7);
|
||||
|
||||
@ -138,8 +138,8 @@ begin
|
||||
end block rx;
|
||||
|
||||
tx : block
|
||||
type state_t is (IDLE, ARP, CALC_CKS, HEADER, PAYLOAD);
|
||||
signal state : state_t;
|
||||
type state_t is (IDLE, ARP, CALC_CKS, HEADER, PAYLOAD);
|
||||
signal state : state_t;
|
||||
|
||||
signal full_length : ipv4_length;
|
||||
|
||||
|
@ -83,8 +83,8 @@ begin
|
||||
end block rx;
|
||||
|
||||
tx : block
|
||||
type state_t is (IDLE, TXD);
|
||||
signal state : state_t;
|
||||
type state_t is (IDLE, TXD);
|
||||
signal state : state_t;
|
||||
|
||||
begin
|
||||
arb : process(clk, rst) is
|
||||
|
@ -41,10 +41,10 @@ begin
|
||||
|
||||
constant HEAD_LENGTH : integer := mac_out.rx_header.mac_destination'length + mac_out.rx_header.mac_source'length + mac_out.rx_header.mac_ethertype'length;
|
||||
constant CRC_LENGTH : integer := 4;
|
||||
signal state : state_t;
|
||||
signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
|
||||
signal state : state_t;
|
||||
signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
|
||||
constant BYTE_COUNT_MAX : integer := maximum(HEAD_LENGTH, CRC_LENGTH) - 1;
|
||||
signal byte_count : integer range 0 to BYTE_COUNT_MAX;
|
||||
signal byte_count : integer range 0 to BYTE_COUNT_MAX;
|
||||
|
||||
signal sr_payload : byte_vector(0 to 4);
|
||||
|
||||
@ -102,7 +102,7 @@ begin
|
||||
byte_count <= byte_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error)
|
||||
when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error)
|
||||
if phy_out.rx_data_valid then
|
||||
sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
|
||||
if byte_count = CRC_LENGTH then
|
||||
@ -136,14 +136,14 @@ begin
|
||||
end block rx;
|
||||
|
||||
tx : block
|
||||
type tx_state_t is (IDLE, HEADER, DATA, PAD, TXCRC);
|
||||
signal tx_state : tx_state_t;
|
||||
type tx_state_t is (IDLE, HEADER, DATA, PAD, TXCRC);
|
||||
signal tx_state : tx_state_t;
|
||||
|
||||
signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1);
|
||||
signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1);
|
||||
constant SR_CNT_MAX : integer := sr'high;
|
||||
signal sr_cnt : integer range 0 to SR_CNT_MAX;
|
||||
signal sr_cnt : integer range 0 to SR_CNT_MAX;
|
||||
constant BYTE_CNT_MAX : integer := ETH_FRAME_MIN_LENGTH - 4; -- Minus four because the CRC is *after* the PAD
|
||||
signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
|
||||
signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
|
||||
|
||||
signal crc : std_logic_vector(ETH_POLYNOMIAL'range);
|
||||
signal crc_clear : std_logic;
|
||||
|
@ -44,7 +44,7 @@ begin
|
||||
|
||||
common : block
|
||||
constant TICK_MS_CNT_MAX : integer := (F_CLK / 1000) - 1;
|
||||
signal tick_ms_count : integer range 0 to TICK_MS_CNT_MAX;
|
||||
signal tick_ms_count : integer range 0 to TICK_MS_CNT_MAX;
|
||||
begin
|
||||
mstick : process(clk, rst) is
|
||||
begin
|
||||
@ -80,7 +80,7 @@ begin
|
||||
|
||||
-- NLP supervision
|
||||
constant NLP_TIMEOUT_CNT_MAX : integer := (16 + 8) - 1; -- Every 16 ms (timebase 1 ms)
|
||||
signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX;
|
||||
signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX;
|
||||
begin
|
||||
-- Synchronize RX input
|
||||
synchronizer_rxp_inst : entity work.synchronizer
|
||||
@ -111,26 +111,26 @@ begin
|
||||
|
||||
demanchestizer : block
|
||||
-- Transition detector
|
||||
constant BIT_LENGTH_LONG : integer := F_CLK / F_ETH - 1;
|
||||
constant BIT_LENGTH_SHORT : integer := F_CLK / (F_ETH * 2) - 1;
|
||||
constant BIT_LENGTH_TOLERANCE : integer := (F_CLK / F_ETH) / 5;
|
||||
constant BIT_LENGTH_TIMEOUT : integer := BIT_LENGTH_LONG + BIT_LENGTH_TOLERANCE + 1;
|
||||
signal sample_count : integer range 0 to BIT_LENGTH_TIMEOUT;
|
||||
type transition_duration_t is (SHORT, LONG);
|
||||
signal transition_duration : transition_duration_t;
|
||||
signal transition_stb : std_logic;
|
||||
signal transition_activity : std_logic;
|
||||
constant BIT_LENGTH_LONG : integer := F_CLK / F_ETH - 1;
|
||||
constant BIT_LENGTH_SHORT : integer := F_CLK / (F_ETH * 2) - 1;
|
||||
constant BIT_LENGTH_TOLERANCE : integer := (F_CLK / F_ETH) / 5;
|
||||
constant BIT_LENGTH_TIMEOUT : integer := BIT_LENGTH_LONG + BIT_LENGTH_TOLERANCE + 1;
|
||||
signal sample_count : integer range 0 to BIT_LENGTH_TIMEOUT;
|
||||
type transition_duration_t is (SHORT, LONG);
|
||||
signal transition_duration : transition_duration_t;
|
||||
signal transition_stb : std_logic;
|
||||
signal transition_activity : std_logic;
|
||||
|
||||
-- Transition analysis
|
||||
signal last_transition : transition_duration_t;
|
||||
type bit_ev_t is (NONE, TOGGLE, KEEP, ERROR);
|
||||
type bit_ev_t is (NONE, TOGGLE, KEEP, ERROR);
|
||||
signal bit_ev : bit_ev_t;
|
||||
|
||||
-- Bit recovery
|
||||
type demanchestization_state_t is (SYNC, DATA, ERROR);
|
||||
signal demanchestization_state : demanchestization_state_t;
|
||||
type demanchestization_state_t is (SYNC, DATA, ERROR);
|
||||
signal demanchestization_state : demanchestization_state_t;
|
||||
constant DEMANCHESTIZATION_MIN_SYNC_CNT_MAX : integer := (4 * 8) - 1; -- 4 good sync bytes
|
||||
signal demanchestization_min_sync_cnt : integer range 0 to DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
|
||||
signal demanchestization_min_sync_cnt : integer range 0 to DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
|
||||
begin
|
||||
-- Detects spacing of transitions
|
||||
transition_detector : process(clk, rst) is
|
||||
@ -253,7 +253,7 @@ begin
|
||||
begin
|
||||
if rst then
|
||||
phy_out.rx_data_valid <= '0';
|
||||
phy_out.rx_data <= (others => '0'); -- Needed for yosys to compile
|
||||
phy_out.rx_data <= (others => '0'); -- Needed for yosys to compile
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
phy_out.rx_data_valid <= '0';
|
||||
@ -301,21 +301,21 @@ begin
|
||||
constant TX_STB_SKIP_ERROR : real := abs (round(TX_STB_CNT_IDEAL) - TX_STB_CNT_IDEAL);
|
||||
constant TX_STB_CNT_MAX : integer := integer(round(TX_STB_CNT_IDEAL + 0.25)) - 1; -- Round up starting for error > 0.25
|
||||
constant TX_STB_SKIP_SECOND : boolean := TX_STB_SKIP_ERROR >= 0.25; -- Skip one clock cycle every other symbol to hit clock rate in between when the divider is close to x.5
|
||||
signal tx_stb_cnt : integer range 0 to TX_STB_CNT_MAX;
|
||||
signal tx_stb_cnt : integer range 0 to TX_STB_CNT_MAX;
|
||||
|
||||
type tx_state_t is (IDLE, NLP, TX, IPG);
|
||||
signal tx_state : tx_state_t;
|
||||
signal sr : std_logic_vector(phy_in.tx_data'range);
|
||||
signal bit_stage : std_logic;
|
||||
type tx_state_t is (IDLE, NLP, TX, IPG);
|
||||
signal tx_state : tx_state_t;
|
||||
signal sr : std_logic_vector(phy_in.tx_data'range);
|
||||
signal bit_stage : std_logic;
|
||||
|
||||
constant BIT_CNT_MAX_IPG : integer := 96;
|
||||
constant BIT_CNT_MAX_DATA : integer := sr'length - 1;
|
||||
signal bit_cnt : integer range 0 to maximum(BIT_CNT_MAX_IPG, BIT_CNT_MAX_DATA);
|
||||
signal bit_cnt : integer range 0 to maximum(BIT_CNT_MAX_IPG, BIT_CNT_MAX_DATA);
|
||||
constant NLP_CNT_MAX : integer := 15; -- specced 16 ms, but there's margin, so let's choose 15 to save a bit (timebase 1 ms)
|
||||
signal nlp_cnt : integer range 0 to NLP_CNT_MAX;
|
||||
signal nlp_cnt : integer range 0 to NLP_CNT_MAX;
|
||||
|
||||
type tx_mode_t is (OFF, NLP, ACTIVE);
|
||||
signal tx_mode : tx_mode_t;
|
||||
type tx_mode_t is (OFF, NLP, ACTIVE);
|
||||
signal tx_mode : tx_mode_t;
|
||||
begin
|
||||
tx_main : process(clk, rst) is
|
||||
procedure transmit_byte is
|
||||
|
@ -14,14 +14,14 @@ use ieee.numeric_std.all;
|
||||
|
||||
package trashernet_pkg is
|
||||
-- General types
|
||||
subtype byte is std_logic_vector(7 downto 0);
|
||||
type byte_vector is array (natural range <>) of byte;
|
||||
subtype byte is std_logic_vector(7 downto 0);
|
||||
type byte_vector is array (natural range <>) of byte;
|
||||
|
||||
-- MAC specific types
|
||||
subtype mac_addr_t is byte_vector(0 to 5);
|
||||
subtype mac_addr_t is byte_vector(0 to 5);
|
||||
constant MAC_ADDR_BROADCAST : mac_addr_t := (others => x"FF");
|
||||
function mac_to_string(constant mac_address : in mac_addr_t) return string;
|
||||
subtype ethertype_t is byte_vector(0 to 1);
|
||||
subtype ethertype_t is byte_vector(0 to 1);
|
||||
|
||||
type mac_header_fields is record
|
||||
mac_destination : mac_addr_t; -- Destination MAC address
|
||||
@ -80,13 +80,13 @@ package trashernet_pkg is
|
||||
end record mac_out_t;
|
||||
|
||||
-- MAC ETH interface
|
||||
type ethernet_ii_protocol_t is record
|
||||
type ethernet_ii_protocol_t is record
|
||||
ethertype : ethertype_t;
|
||||
end record;
|
||||
type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
|
||||
constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic
|
||||
constant ETHERNET_II_PROTOCOL_IPV4 : ethernet_ii_protocol_t := (ethertype => (x"08", x"00"));
|
||||
constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06"));
|
||||
type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
|
||||
constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic
|
||||
constant ETHERNET_II_PROTOCOL_IPV4 : ethernet_ii_protocol_t := (ethertype => (x"08", x"00"));
|
||||
constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06"));
|
||||
|
||||
type ethernet_i_out_t is record
|
||||
rx_mac_address : mac_addr_t; -- Source MAC address
|
||||
@ -121,9 +121,9 @@ package trashernet_pkg is
|
||||
tx_data : byte; -- TX data
|
||||
tx_en : std_logic; -- Start and continue transmitting
|
||||
end record;
|
||||
type ethernet_ii_out_vector is array (natural range <>) of ethernet_ii_out_t;
|
||||
type ethernet_ii_in_vector is array (natural range <>) of ethernet_ii_in_t;
|
||||
constant ETHERNET_II_IN_UNUSED : ethernet_ii_in_t := (tx_mac_address => (others => x"00"), tx_data => x"00", others => '0');
|
||||
type ethernet_ii_out_vector is array (natural range <>) of ethernet_ii_out_t;
|
||||
type ethernet_ii_in_vector is array (natural range <>) of ethernet_ii_in_t;
|
||||
constant ETHERNET_II_IN_UNUSED : ethernet_ii_in_t := (tx_mac_address => (others => x"00"), tx_data => x"00", others => '0');
|
||||
|
||||
-- ARP interface
|
||||
type arp_out_t is record
|
||||
@ -137,12 +137,12 @@ package trashernet_pkg is
|
||||
end record arp_in_t;
|
||||
|
||||
-- IPv4 interface
|
||||
subtype ipv4_protocol is byte;
|
||||
type ipv4_protocol_vector is array (natural range <>) of ipv4_protocol;
|
||||
constant IPV4_PROTOCOL_ICMP : ipv4_protocol := x"01";
|
||||
constant IPV4_PROTOCOL_TCP : ipv4_protocol := x"06";
|
||||
constant IPV4_PROTOCOL_UDP : ipv4_protocol := x"11";
|
||||
subtype ipv4_length is unsigned(15 downto 0);
|
||||
subtype ipv4_protocol is byte;
|
||||
type ipv4_protocol_vector is array (natural range <>) of ipv4_protocol;
|
||||
constant IPV4_PROTOCOL_ICMP : ipv4_protocol := x"01";
|
||||
constant IPV4_PROTOCOL_TCP : ipv4_protocol := x"06";
|
||||
constant IPV4_PROTOCOL_UDP : ipv4_protocol := x"11";
|
||||
subtype ipv4_length is unsigned(15 downto 0);
|
||||
|
||||
type ipv4_out_t is record
|
||||
rx_ip_address : ip_addr_t; -- Source IP address
|
||||
@ -189,12 +189,12 @@ package trashernet_pkg is
|
||||
tx_en : std_logic; -- Start and continue transmitting
|
||||
end record ipv4_protocol_in_t;
|
||||
type ipv4_protocol_out_vector is array (natural range <>) of ipv4_protocol_out_t;
|
||||
type ipv4_protocol_in_vector is array (natural range <>) of ipv4_protocol_in_t;
|
||||
type ipv4_protocol_in_vector is array (natural range <>) of ipv4_protocol_in_t;
|
||||
|
||||
-- UDP interface
|
||||
subtype udp_port_t is unsigned(15 downto 0);
|
||||
subtype udp_port_t is unsigned(15 downto 0);
|
||||
subtype udp_length_t is unsigned(15 downto 0);
|
||||
type udp_out_t is record
|
||||
type udp_out_t is record
|
||||
rx_data : byte; -- RX Data
|
||||
rx_data_valid : std_logic; -- RX data valid strobe
|
||||
|
||||
@ -220,20 +220,20 @@ package trashernet_pkg is
|
||||
tx_data : byte;
|
||||
end record udp_in_t;
|
||||
|
||||
type udpprot_rx_out_t is record
|
||||
type udpprot_rx_out_t is record
|
||||
temp : std_logic;
|
||||
end record udpprot_rx_out_t;
|
||||
type udpprot_rx_in_t is record
|
||||
type udpprot_rx_in_t is record
|
||||
temp : std_logic;
|
||||
end record udpprot_rx_in_t;
|
||||
type udpprot_tx_out_t is record
|
||||
type udpprot_tx_out_t is record
|
||||
temp : std_logic;
|
||||
end record udpprot_tx_out_t;
|
||||
type udpprot_tx_in_t is record
|
||||
type udpprot_tx_in_t is record
|
||||
temp : std_logic;
|
||||
end record udpprot_tx_in_t;
|
||||
subtype portnum is integer range 0 to 65535;
|
||||
type udp_port_vector is array (natural range <>) of portnum;
|
||||
subtype portnum is integer range 0 to 65535;
|
||||
type udp_port_vector is array (natural range <>) of portnum;
|
||||
|
||||
-- General helper functions
|
||||
function to_std_logic(constant bool : boolean) return std_logic;
|
||||
|
Loading…
x
Reference in New Issue
Block a user