trashernet/cocotb/cocotb_top_hwitl.vhd

-- -------------------------------------------------------------------------- --
--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
-- -------------------------------------------------------------------------- --
-- cocotb_top_hwitl.vhd : Test bench for cocotb HW-in-the-loop tests
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library design;
use design.all;

entity cocotb_top_hwitl is
end entity cocotb_top_hwitl;

architecture bench of cocotb_top_hwitl is
	-- DUT signals
	signal clk        : std_logic;
	signal rst_n      : std_logic;
	signal rx_p       : std_logic;
	signal tx_p       : std_logic;
	signal tx_n       : std_logic;
	signal led_n      : std_logic_vector(7 downto 0);
	signal button_n   : std_logic_vector(3 downto 0);
	signal debug_data : std_logic_vector(7 downto 0);

	-- Generic test bench
	signal bench_ready : std_logic := '0';
begin
	top_mac_test_inst : entity top_hwitl(eth) -- TODO: I haven't managed to get configurations working with cocotb yet, so changing this line changes the test case :(
		port map(
			clk        => clk,
			rst_n      => rst_n,
			rx_p       => rx_p,
			tx_p       => tx_p,
			tx_n       => tx_n,
			led_n      => led_n,
			button_n   => button_n,
			debug_data => debug_data
		);

	clock_driver : process
		constant period : time := 20 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	rstsim : process is
	begin
		rst_n       <= '0';
		wait for 400 ns;
		rst_n       <= '1';
		wait for 100 ns;
		wait until rising_edge(clk);
		bench_ready <= '1';
		wait;
	end process rstsim;

	cocovc_eth_inst : entity work.cocovc_eth
		port map(
			rx_p => tx_p,
			rx_n => tx_n,
			tx_p => rx_p,
			tx_n => open
		);

	test_seq : process is
	begin
		wait until bench_ready = '1';

		button_n <= (others => '1');
		wait for 1 us;

		wait until rising_edge(clk);
		button_n(0) <= '0';
		wait until rising_edge(clk);
		button_n(0) <= '1';

		wait;
	end process test_seq;

end architecture bench;