trashernet/bench/bench_crc.vhd

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2.2 KiB
VHDL
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-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- bench_crc.vhd : Stimulus-only test bench for the CRC
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library trashernet;
entity bench_crc is
end entity bench_crc;
architecture bench of bench_crc is
constant POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7";
signal clk : std_logic;
signal rst : std_logic;
signal data : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal crc_clear : std_logic;
signal crc_out : std_logic_vector(POLYNOMIAL'range);
begin
crc_inst : entity trashernet.crc
generic map(
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POLYNOMIAL => POLYNOMIAL,
START => x"FFFFFFFF",
FINAL_XOR => x"FFFFFFFF",
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REVERSE_OUT => true
)
port map(
clk => clk,
rst => rst,
data => data,
data_valid => data_valid,
crc_clear => crc_clear,
crc_out => crc_out
);
clock_driver : process
constant period : time := 10 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
test : process is
procedure send_byte(b : std_logic_vector(data'range)) is
begin
data <= b;
data_valid <= '1';
wait until rising_edge(clk);
data_valid <= '0';
end procedure send_byte;
variable temp : std_logic_vector(crc_out'range);
begin
rst <= '1';
data_valid <= '0';
crc_clear <= '0';
wait for 20 ns;
rst <= '0';
wait until rising_edge(clk);
send_byte(x"01");
wait until rising_edge(clk);
report "CRC: " & to_hstring(crc_out);
for i in 31 downto 0 loop
temp(i) := crc_out(31 - i);
end loop;
report "BITREV: " & to_hstring(temp);
wait;
end process test;
end architecture bench;