trashernet/trashernet/synchronizer.vhd

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VHDL
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2021-08-27 20:11:07 +02:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
port(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end entity synchronizer;
architecture RTL of synchronizer is
signal sr : std_logic_vector(2 downto 0);
begin
sync : process(clk, rst) is
begin
if rst then
sr <= (others => '0');
elsif rising_edge(clk) then
sr <= sr(sr'high - 1 downto sr'low) & data_in;
end if;
end process sync;
data_out <= sr(sr'high);
end architecture RTL;