27 lines
559 B
VHDL
27 lines
559 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity synchronizer is
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port(
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clk : in std_logic;
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rst : in std_logic;
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data_in : in std_logic;
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data_out : out std_logic
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);
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end entity synchronizer;
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architecture RTL of synchronizer is
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signal sr : std_logic_vector(2 downto 0);
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begin
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sync : process(clk, rst) is
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begin
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if rst then
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sr <= (others => '0');
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elsif rising_edge(clk) then
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sr <= sr(sr'high - 1 downto sr'low) & data_in;
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end if;
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end process sync;
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data_out <= sr(sr'high);
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end architecture RTL;
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