Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers, including physical!
trashernet | ||
README.MD |
Trashernet
Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:
- Layer 1, Physical:
trashernet_phy
- Layer 2, Data link:
trashernet_mac
When writing it, the following were the main design philosophies:
- Standards are nice and all, but this, it just needs to work.
- Hardware is expensive, LOC are not. So let's do everything we can inside the FPGA.
- If there's a feature that feels optional even though it isn't, it is. See 1. if in doubt.
IMPORTANT: This code (and HW suggestions) violate the Ethernet standard in many ways. Do not use in proper (especially commercial) products.
Hardware
TBD. TL;DR:
- RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL.
- TX: Meh, a series current limiting resistor is good enough.
License
This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.