Fix code formatting

bench/bench_crc.vhd

@@ -28,9 +28,9 @@ architecture bench of bench_crc is
 begin
 	crc_inst : entity trashernet.crc
 		generic map(
-			POLYNOMIAL => POLYNOMIAL,
-			START => x"FFFFFFFF",
-			FINAL_XOR => x"FFFFFFFF",
+			POLYNOMIAL  => POLYNOMIAL,
+			START       => x"FFFFFFFF",
+			FINAL_XOR   => x"FFFFFFFF",
 			REVERSE_OUT => true
 		)
 		port map(

trashernet/trashernet_phy_cdc.vhd

@@ -27,11 +27,11 @@ entity trashernet_phy_cdc is
 		rst            : in  std_logic; -- Asynchronous reset
 
 		-- System interface
-		rx_data        : out byte; -- RX Data
+		rx_data        : out byte;      -- RX Data
 		rx_data_valid  : out std_logic; -- RX Data valid
 		rx_active      : out std_logic; -- RX of packet in progress
 
-		tx_data        : in  byte; -- TX Data
+		tx_data        : in  byte;      -- TX Data
 		tx_data_en     : in  std_logic; -- Transmitter enable
 		tx_data_ack    : out std_logic; -- Latched data_tx
 		tx_active      : out std_logic; -- Transmission in progress