fpga/trashernet
1
0
Fork 0
Code Issues 7 Pull Requests 2 Releases 2 Wiki Activity

bench: hw_itl: Calculate and append FCS for incoming frames

Browse Source
This commit is contained in:
Markus Koch 2022-05-13 18:20:13 +02:00
parent 0e80900426
commit 4b4e5fdbfa
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
cocotb/hw_itl.py
View File

@ -13,6 +13,7 @@ import time
import os import os
import asyncio import asyncio
import fcntl import fcntl
import zlib
''' '''
# Set up virtual device using # Set up virtual device using
@ -37,11 +38,18 @@ class MacDevReceiver():
self.macdev.bind((dev, 0)) self.macdev.bind((dev, 0))
fcntl.fcntl(self.macdev, fcntl.F_SETFL, os.O_NONBLOCK) # Not the best way to poll, but I couldn't get asyncio to play nicely with threading... fcntl.fcntl(self.macdev, fcntl.F_SETFL, os.O_NONBLOCK) # Not the best way to poll, but I couldn't get asyncio to play nicely with threading...
def eth_fcs(self, data):
crc = zlib.crc32(data) & 0xFFFF_FFFF
return crc.to_bytes(4, byteorder='little')
async def main(self): async def main(self):
ETH_HEAD = b'\x55\x55\x55\x55\xD5' ETH_HEAD = b'\x55\x55\x55\x55\xD5'
while True: while True:
try: try:
r = self.macdev.recv(2000) r = self.macdev.recv(2000)
if len(r) < 60:
r += b'\x00' * (60 - len(r))
r += self.eth_fcs(r)
await self.eth_tx.send(ETH_HEAD + r); await self.eth_tx.send(ETH_HEAD + r);
except: except:
await Timer(1, "us") await Timer(1, "us")