fpga/trashernet
1
0
Fork 0
Code Issues 7 Pull Requests 2 Releases 2 Wiki Activity

phy: rx: Introduce simple glitch filter

Browse Source
This commit is contained in:
Markus Koch 2021-08-28 14:22:28 +02:00
parent 08bd5f166b
commit 5d6df0219b
1 changed files with 21 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
trashernet/trashernet_phy.vhd
View File

@ -37,9 +37,10 @@ begin
receiver : block receiver : block
-- Signal conditioning -- Signal conditioning
signal rx : std_logic; signal rx : std_logic;
signal rx_last : std_logic; signal rx_last : std_logic;
signal rx_edge : std_logic; signal rx_last_static : std_logic;
signal rx_edge : std_logic;
-- Bit recovery -- Bit recovery
signal bit_value : std_logic; signal bit_value : std_logic;
@ -61,11 +62,23 @@ begin
data_out => rx data_out => rx
); );
-- Edge detector for RX -- Edge detector for RX (+glitch filter)
rx_last <= '0' when rst edgedet : process(clk, rst) is
else rx when rising_edge(clk) begin
; if rst then
rx_edge <= rx_last xor rx; rx_last <= '0';
rx_last_static <= '0';
rx_edge <= '0';
elsif rising_edge(clk) then
rx_edge <= '0';
if (rx_last = rx) then
rx_edge <= rx_last_static xor rx;
rx_last_static <= rx;
end if;
rx_last <= rx;
end if;
end process edgedet;
demanchestizer : block demanchestizer : block
-- Transition detector -- Transition detector