icmp: Implement ICMP echo replies
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parent
87bc9ce3d7
commit
6de8d24537
@ -226,6 +226,14 @@ architecture eth of top_hwitl is
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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begin
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begin
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trashernet_icmp_inst : entity trashernet.trashernet_icmp
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port map(
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clk => clk,
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rst => rst,
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ipv4_protocol_out => ipv4_protocol_out(IPROT_ICMP),
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ipv4_protocol_in => ipv4_protocol_in(IPROT_ICMP)
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);
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trashernet_ipv4prot_inst : entity trashernet.trashernet_ipv4prot
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trashernet_ipv4prot_inst : entity trashernet.trashernet_ipv4prot
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generic map(
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generic map(
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IPV4_PROTOCOLS => IPV4_PROTOCOLS
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IPV4_PROTOCOLS => IPV4_PROTOCOLS
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@ -344,13 +352,7 @@ begin
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if (ethernet_ii_out(PROT_ARP).rx_header_rcv) then
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if (ethernet_ii_out(PROT_ARP).rx_header_rcv) then
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report "RX ARP";
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report "RX ARP";
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end if;
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end if;
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if (ethernet_ii_out(PROT_IPV4).rx_header_rcv) then
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report "RX IP";
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end if;
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if ipv4_out.rx_data_valid then
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report "RX IP data: " & to_hstring(ipv4_out.rx_data);
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end if;
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if ipv4_out.rx_ok_stb then
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if ipv4_out.rx_ok_stb then
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report "RX IP OK";
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report "RX IP OK";
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end if;
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end if;
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98
trashernet/fifo.vhd
Normal file
98
trashernet/fifo.vhd
Normal file
@ -0,0 +1,98 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- fifo.vhd : Basic single-clock FIFO
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-- Implements a basic single-clock FIFO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fifo is
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generic(
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DEPTH : natural -- Number of elements the FIFO can hold
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);
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- FIFO
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clear : in std_logic; -- Synchronous reset (clear FIFO)
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data_in : in std_logic_vector; -- Data into the FIFO (automatically constrains width)
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push : in std_logic; -- Push `data_in` into the FIFO
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full : out std_logic; -- No further elements can be pushed into the FIFO
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data_out : out std_logic_vector; -- Data out of the FIFO
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pop : in std_logic; -- Get an element from the FIFO
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empty : out std_logic -- FIFO is empty
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);
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end entity fifo;
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architecture rtl of fifo is
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type memory_t is array (natural range <>) of std_logic_vector(data_in'range);
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signal memory : memory_t(0 to DEPTH - 1);
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subtype memory_pointer_t is integer range 0 to DEPTH - 1;
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subtype usage_counter_t is integer range 0 to DEPTH;
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signal read_pointer : memory_pointer_t;
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signal write_pointer : memory_pointer_t;
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signal usage_counter : usage_counter_t;
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begin
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fifo_proc : process(clk, rst) is
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procedure increment_pointer(signal pointer : inout memory_pointer_t) is
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begin
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if pointer = pointer'subtype'high then
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pointer <= 0;
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else
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pointer <= pointer + 1;
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end if;
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end procedure increment_pointer;
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variable pushed : boolean;
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variable popped : boolean;
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begin
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if rst then
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read_pointer <= 0;
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write_pointer <= 0;
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usage_counter <= 0;
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elsif rising_edge(clk) then
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pushed := false;
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popped := false;
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if push and not full then
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memory(write_pointer) <= data_in;
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increment_pointer(write_pointer);
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usage_counter <= usage_counter + 1;
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pushed := true;
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end if;
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if pop and not empty then
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increment_pointer(read_pointer);
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usage_counter <= usage_counter - 1;
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popped := true;
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end if;
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if pushed and popped then
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usage_counter <= usage_counter;
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end if;
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if clear then
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read_pointer <= 0;
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write_pointer <= 0;
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usage_counter <= 0;
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end if;
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end if;
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end process fifo_proc;
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data_out <= memory(read_pointer);
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empty <= '1' when usage_counter = 0 else '0';
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full <= '1' when usage_counter = DEPTH else '0';
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end architecture rtl;
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172
trashernet/trashernet_icmp.vhd
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172
trashernet/trashernet_icmp.vhd
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@ -0,0 +1,172 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- trashernet_icmp.vhd : Ethernet OSI Layer 3, Network (ICMP)
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-- Implements ICMP echo replies
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.trashernet_pkg.all;
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entity trashernet_icmp is
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- IPv4 application interface
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ipv4_protocol_out : in ipv4_protocol_out_t; -- IPv4 Protocol IF (out from IP Mux)
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ipv4_protocol_in : out ipv4_protocol_in_t -- IPv4 Protocol IF (into IP Mux)
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);
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end entity trashernet_icmp;
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architecture rtl of trashernet_icmp is
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signal fifo_clear : std_logic;
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signal fifo_data_in : std_logic_vector(byte'range);
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signal fifo_push : std_logic;
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signal fifo_full : std_logic; -- TODO: FIFO full error handling
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signal fifo_data_out : std_logic_vector(fifo_data_in'range);
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signal fifo_pop : std_logic;
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signal fifo_empty : std_logic;
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signal tx_response : std_logic;
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signal rx_checksum : std_logic_vector(15 downto 0);
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begin
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fifo_inst : entity work.fifo
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generic map(
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DEPTH => 64
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)
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port map(
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clk => clk,
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rst => rst,
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clear => fifo_clear,
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data_in => fifo_data_in,
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push => fifo_push,
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full => fifo_full,
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data_out => fifo_data_out,
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pop => fifo_pop,
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empty => fifo_empty
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);
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rx : block
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signal sr : byte_vector(0 to 3);
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alias sr_type is sr(0);
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alias sr_code is sr(1);
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alias sr_checksum is sr(2 to 3);
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type state_t is (HEADER, DATA, IGNORE);
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signal state : state_t;
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signal byte_count : integer range 0 to sr'length;
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begin
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rx_fsm : process(clk, rst) is
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begin
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if rst then
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state <= HEADER;
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byte_count <= byte_count'subtype'high;
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elsif rising_edge(clk) then
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if (ipv4_protocol_out.rx_data_valid = '1') and (byte_count /= 0) then
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byte_count <= byte_count - 1;
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if state = HEADER then
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sr <= sr(sr'low + 1 to sr'high) & ipv4_protocol_out.rx_data;
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end if;
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end if;
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if ipv4_protocol_out.rx_header_rcv then
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byte_count <= byte_count'subtype'high;
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state <= HEADER;
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end if;
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case state is
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when HEADER =>
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if byte_count = 0 then
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if sr_type = x"08" then
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state <= DATA;
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else
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state <= IGNORE;
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end if;
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end if;
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when DATA =>
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null; -- We just wait here and collect data
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when IGNORE => -- Just wait until it's over
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null;
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end case;
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end if;
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end process rx_fsm;
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fifo_clear <= ipv4_protocol_out.rx_header_rcv; -- TODO: This will break things when we get another Ping too soon
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fifo_push <= ipv4_protocol_out.rx_data_valid when state = DATA else '0';
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fifo_data_in <= ipv4_protocol_out.rx_data;
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tx_response <= ipv4_protocol_out.rx_ok_stb when state = DATA else '0';
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rx_checksum <= sr_checksum(2) & sr_checksum(3);
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end block rx;
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tx : block
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signal checksum : unsigned(16 downto 0);
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signal checksum_ones : unsigned(15 downto 0);
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type state_t is (IDLE, HEADER, PAYLOAD);
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signal state : state_t;
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signal sr : byte_vector(0 to 3);
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signal byte_count : integer range 0 to sr'subtype'high;
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begin
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checksum <= ('0' & not (unsigned(rx_checksum))) - unsigned'('0' & x"0800"); -- The only change is Type 8 changes to Type 0
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checksum_ones <= not (checksum(15 downto 0) - checksum(16));
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tx_fsm : process(clk, rst) is
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begin
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if rst then
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elsif rising_edge(clk) then
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if (ipv4_protocol_out.tx_data_ack = '1') and (byte_count /= 0) then
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sr <= sr(sr'low + 1 to sr'high) & x"00";
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byte_count <= byte_count - 1;
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end if;
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case state is
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when IDLE =>
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if tx_response then
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ipv4_protocol_in.tx_ip_address <= ipv4_protocol_out.rx_ip_address; -- TODO: This is technically too late, but ¯\_(ツ)_/¯
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ipv4_protocol_in.tx_length <= ipv4_protocol_out.rx_length;
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sr <= byte_vector'(
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x"00",
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x"00",
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std_logic_vector(checksum_ones(15 downto 8)),
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std_logic_vector(checksum_ones(7 downto 0))
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);
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byte_count <= sr'subtype'high;
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state <= HEADER;
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end if;
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when HEADER =>
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if (byte_count = 0) and (ipv4_protocol_out.tx_data_ack = '1') then
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state <= PAYLOAD;
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end if;
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when PAYLOAD =>
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if fifo_empty then
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state <= IDLE;
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end if;
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end case;
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end if;
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end process tx_fsm;
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fifo_pop <= ipv4_protocol_out.tx_data_ack when state = PAYLOAD else '0';
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ipv4_protocol_in.tx_en <= '1' when (state = HEADER) or (state = PAYLOAD) else '0';
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ipv4_protocol_in.tx_data <= sr(sr'low) when state = HEADER else fifo_data_out;
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end block tx;
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end architecture rtl;
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