doc: Add trashernet_eth to documentation
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Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:
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* Layer 1, Physical: `trashernet_phy`
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* Layer 2, Data link: `trashernet_mac`
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* Layer 2, Data link: `trashernet_mac`, `trashernet_eth`
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When writing it, the following were the main design philosophies:
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