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mac: Refactor incorrect signal name

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This commit is contained in:
Markus Koch 2022-01-16 13:43:55 +01:00
parent 18b4213ed0
commit 97d0905c08
1 changed files with 9 additions and 9 deletions
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18
trashernet/trashernet_mac.vhd
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@ -139,7 +139,7 @@ begin
signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1); signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1);
constant BIT_CNT_MAX : integer := sr'high; constant BIT_CNT_MAX : integer := sr'high;
signal byte_cnt : integer range 0 to BIT_CNT_MAX; signal bit_cnt : integer range 0 to BIT_CNT_MAX;
signal crc : std_logic_vector(ETH_POLYNOMIAL'range); signal crc : std_logic_vector(ETH_POLYNOMIAL'range);
signal crc_clear : std_logic; signal crc_clear : std_logic;
@ -173,40 +173,40 @@ begin
if phy_out.tx_data_ack then if phy_out.tx_data_ack then
sr <= sr(sr'low + 1 to sr'high) & x"00"; sr <= sr(sr'low + 1 to sr'high) & x"00";
crc_valid <= '1'; crc_valid <= '1';
if byte_cnt /= 0 then if bit_cnt /= 0 then
byte_cnt <= byte_cnt - 1; bit_cnt <= bit_cnt - 1;
end if; end if;
end if; end if;
case tx_state is case tx_state is
when IDLE => when IDLE =>
if not phy_out.tx_active and mac_in.tx_mac_data_en then if not phy_out.tx_active and mac_in.tx_mac_data_en then
sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5"); sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
byte_cnt <= 7; bit_cnt <= 7;
tx_state <= HEADER; tx_state <= HEADER;
end if; end if;
when HEADER => when HEADER =>
if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete if (phy_out.tx_data_ack = '1') and (bit_cnt = 0) then -- Sync Header TX complete
sr <= mac_in.tx_header.mac_destination & mac_in.tx_header.mac_source & mac_in.tx_header.mac_ethertype; sr <= mac_in.tx_header.mac_destination & mac_in.tx_header.mac_source & mac_in.tx_header.mac_ethertype;
crc_valid <= '1'; crc_valid <= '1';
byte_cnt <= BIT_CNT_MAX; bit_cnt <= BIT_CNT_MAX;
tx_state <= DATA; tx_state <= DATA;
end if; end if;
when DATA => when DATA =>
if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete if (phy_out.tx_data_ack = '1') and (bit_cnt = 0) then -- MAC Header TX complete
if mac_in.tx_mac_data_en then if mac_in.tx_mac_data_en then
sr(0) <= mac_in.tx_mac_data; sr(0) <= mac_in.tx_mac_data;
mac_out.tx_mac_data_ack <= '1'; mac_out.tx_mac_data_ack <= '1';
else else
sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24)); sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24));
byte_cnt <= 4 - 1; bit_cnt <= 4 - 1;
tx_state <= TXCRC; tx_state <= TXCRC;
end if; end if;
end if; end if;
when TXCRC => when TXCRC =>
if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete if (phy_out.tx_data_ack = '1') and (bit_cnt = 0) then -- CRC TX complete
tx_state <= IDLE; tx_state <= IDLE;
end if; end if;
end case; end case;