gen: Add generic timer module

trashernet/timer.vhd

@@ -0,0 +1,64 @@
+-- -------------------------------------------------------------------------- --
+--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
+-- -------------------------------------------------------------------------- --
+-- timer.vhd : Simple Timer
+--   Implements a very simple integer timer
+-- -------------------------------------------------------------------------- --
+-- Author       : Markus Koch <markus@notsyncing.net>
+-- Contributors : None
+-- License      : Mozilla Public License (MPL) Version 2
+-- -------------------------------------------------------------------------- --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity timer is
+	generic(
+		F_TICK    : integer;            -- Frequency of `tick` (or `clk` if tick is tied to '1')
+		DURATION  : time;               -- Duration of the timer
+		AUTOSTART : boolean := false    -- Automatically start the timer after reset
+	);
+	port(
+		clk         : in  std_logic;    -- Global clock
+		rst         : in  std_logic;    -- Asynchronous reset
+
+		tick        : in  std_logic;    -- Timer enable
+		start       : in  std_logic;    -- (Re-)start timer
+
+		expired     : out std_logic;    -- Timer is expired
+		expired_stb : out std_logic     -- Strobe when timer reaches zero
+	);
+end entity timer;
+
+architecture rtl of timer is
+	constant PERIOD : time    := 1 sec / real(F_TICK);
+	constant TICKS  : integer := integer(DURATION / PERIOD);
+
+	signal counter : integer range 0 to TICKS;
+begin
+	timer_p : process(clk, rst) is
+	begin
+		if rst then
+			counter     <= TICKS when AUTOSTART else 0;
+			expired_stb <= '0';
+
+		elsif rising_edge(clk) then
+			expired_stb <= '0';
+			if tick then
+				if counter = 1 then
+					expired_stb <= '1';
+				end if;
+				if counter /= 0 then
+					counter <= counter - 1;
+				end if;
+			end if;
+
+			if start then
+				counter <= TICKS;
+			end if;
+		end if;
+	end process timer_p;
+
+	expired <= not start when counter = 0 else '0';
+end architecture rtl;