fpga/trashernet
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phy+mac: Improve interface

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Instead of having the user wait until the en-low was latched by
the core, let's just latch it internally.
This commit is contained in:
Markus Koch 2022-01-23 16:52:05 +01:00
parent 4a39c3d638
commit a9039a175c
2 changed files with 10 additions and 5 deletions
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5
trashernet/trashernet_mac.vhd
View File

@ -166,6 +166,7 @@ begin
); );
tx_main : process(clk, rst) is tx_main : process(clk, rst) is
variable more_data : std_logic;
begin begin
if rst then if rst then
mac_out.tx_mac_data_ack <= '0'; mac_out.tx_mac_data_ack <= '0';
@ -176,6 +177,7 @@ begin
elsif rising_edge(clk) then elsif rising_edge(clk) then
mac_out.tx_mac_data_ack <= '0'; mac_out.tx_mac_data_ack <= '0';
crc_valid <= '0'; crc_valid <= '0';
more_data := more_data and mac_in.tx_mac_data_en; -- Latch a short low-pulse on tx_en
if phy_out.tx_data_ack then if phy_out.tx_data_ack then
sr <= sr(sr'low + 1 to sr'high) & x"00"; sr <= sr(sr'low + 1 to sr'high) & x"00";
@ -190,6 +192,7 @@ begin
case tx_state is case tx_state is
when IDLE => -- Idle + prepare sync header when IDLE => -- Idle + prepare sync header
if not phy_out.tx_active and mac_in.tx_mac_data_en then if not phy_out.tx_active and mac_in.tx_mac_data_en then
more_data := '1';
sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5"); sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
sr_cnt <= 7; sr_cnt <= 7;
tx_state <= HEADER; tx_state <= HEADER;
@ -206,7 +209,7 @@ begin
when DATA => -- Wait for MAC header + transmit payload until tx_mac_data_en goes away when DATA => -- Wait for MAC header + transmit payload until tx_mac_data_en goes away
if (phy_out.tx_data_ack = '1') and (sr_cnt = 0) then -- MAC Header TX complete if (phy_out.tx_data_ack = '1') and (sr_cnt = 0) then -- MAC Header TX complete
if mac_in.tx_mac_data_en then if more_data then
sr(0) <= mac_in.tx_mac_data; sr(0) <= mac_in.tx_mac_data;
mac_out.tx_mac_data_ack <= '1'; mac_out.tx_mac_data_ack <= '1';
else else

10
trashernet/trashernet_phy.vhd
View File

@ -293,9 +293,8 @@ begin
tx_state <= IPG; tx_state <= IPG;
tx_mode <= OFF; tx_mode <= OFF;
bit_cnt <= BIT_CNT_MAX_IPG; bit_cnt <= BIT_CNT_MAX_IPG;
bit_stage <= '0'; bit_stage <= '0';
phy_out.tx_data_ack <= '1'; -- Notify that the end-of-packet has been accepted
end procedure transmit_ipg; end procedure transmit_ipg;
procedure transmit_nlp is procedure transmit_nlp is
@ -315,6 +314,7 @@ begin
variable tx_stb : std_logic; -- Strobe every 50 ns (20 MHz) variable tx_stb : std_logic; -- Strobe every 50 ns (20 MHz)
variable more_data : std_logic; -- tx_data_en low-latched
begin begin
if rst then if rst then
phy_out.tx_data_ack <= '0'; phy_out.tx_data_ack <= '0';
@ -326,6 +326,7 @@ begin
elsif rising_edge(clk) then elsif rising_edge(clk) then
phy_out.tx_data_ack <= '0'; phy_out.tx_data_ack <= '0';
more_data := more_data and phy_in.tx_data_en; -- Latch a short low-pulse on tx_en
if tx_stb_cnt = 0 then if tx_stb_cnt = 0 then
tx_stb_cnt <= TX_STB_CNT_MAX; tx_stb_cnt <= TX_STB_CNT_MAX;
@ -347,6 +348,7 @@ begin
when IDLE => when IDLE =>
if phy_in.tx_data_en then -- New packet to TX if phy_in.tx_data_en then -- New packet to TX
transmit_byte; transmit_byte;
more_data := '1';
bit_stage <= '1'; bit_stage <= '1';
tx_stb_cnt <= TX_STB_CNT_MAX; -- resync tx_stb_cnt <= TX_STB_CNT_MAX; -- resync
@ -366,7 +368,7 @@ begin
if (bit_stage = '1') then if (bit_stage = '1') then
sr <= '0' & sr(sr'high downto sr'low + 1); sr <= '0' & sr(sr'high downto sr'low + 1);
if bit_cnt = 0 then if bit_cnt = 0 then
if phy_in.tx_data_en then if more_data then
transmit_byte; transmit_byte;
else else
transmit_ipg; transmit_ipg;