rmii: Fix CDC for *_active
On the TX side, we forgot to sync it entirely. For RX, we need to delay the rx_active signal a bit to make sure that it does not get negated before the last _valid strobe.
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@ -138,7 +138,7 @@ begin
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-- CDC
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synchronizer_inst : entity work.synchronizer
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generic map(
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SIZE => 2
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SIZE => 4
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)
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port map(
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clk => clk,
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@ -181,6 +181,7 @@ begin
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signal temp_tx_data : byte;
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signal temp_tx_data_en : std_logic;
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signal temp_tx_data_ack : std_logic;
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signal temp_tx_active : std_logic;
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type state_t is (IDLE, DATA, IPG);
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signal state : state_t;
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@ -201,8 +202,10 @@ begin
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begin
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if rst then
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phy_out.tx_data_ack <= '0';
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phy_out.tx_active <= '0';
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elsif rising_edge(clk) then
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phy_out.tx_data_ack <= temp_tx_data_ack;
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phy_out.tx_active <= temp_tx_active;
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end if;
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end process phy_out_reg;
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@ -233,6 +236,18 @@ begin
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b_rst => rst,
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b_out => phy_out.tx_data_ack
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);
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synchronizer_inst : entity work.synchronizer
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generic map(
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SIZE => 2
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)
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port map(
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clk => clk,
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rst => rst,
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data_in => temp_tx_active,
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data_out => phy_out.tx_active
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);
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end generate cdc_or_register;
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txp : process(rmii_ref_clk, rmii_rst) is
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@ -255,7 +270,7 @@ begin
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case state is
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when IDLE =>
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sr <= temp_tx_data;
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sr <= temp_tx_data;
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dibit_cnt <= 0;
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if temp_tx_data_en then
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state <= DATA;
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@ -277,10 +292,10 @@ begin
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end case;
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end if;
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end process txp;
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byte_done <= '1' when dibit_cnt = 3 else '0';
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block_done <= '1' when (byte_cnt = 0) and (byte_done = '1') else '0';
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temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0';
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phy_out.tx_active <= '1' when state = DATA else '0';
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byte_done <= '1' when dibit_cnt = 3 else '0';
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block_done <= '1' when (byte_cnt = 0) and (byte_done = '1') else '0';
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temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0';
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temp_tx_active <= '1' when state = DATA else '0';
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rmii_txd <= sr(1 downto 0);
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rmii_tx_en <= '1' when state = DATA else '0';
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