Fix linter warnings

feature/arp
Markus Koch 2022-10-30 17:29:14 +01:00
parent 8d9ca9e784
commit ccb7d6c0da
5 changed files with 22 additions and 15 deletions

View File

@ -26,9 +26,9 @@ entity top_hwitl is
rx_p : in std_logic;
tx_p : out std_logic;
tx_n : out std_logic;
led_n : out std_logic_vector(7 downto 0);
button_n : in std_logic_vector(3 downto 0);
debug_data : out std_logic_vector(7 downto 0)
led_n : out std_logic_vector(7 downto 0); -- @suppress: Used in different architectures
button_n : in std_logic_vector(3 downto 0); -- @suppress: Used in different architectures
debug_data : out std_logic_vector(7 downto 0) -- @suppress: Used in different architectures
);
end entity top_hwitl;
@ -48,9 +48,8 @@ architecture mac of top_hwitl is
mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
);
signal rst : std_logic;
signal clk_phy : std_logic;
signal phy_pll_lock : std_logic;
signal rst : std_logic;
signal clk_phy : std_logic;
signal phy_out : phy_out_t;
signal phy_in : phy_in_t;
@ -80,7 +79,7 @@ begin
port map(
CLK => clk,
CLKOP => clk_phy,
LOCK => phy_pll_lock
LOCK => open
);
trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
@ -190,9 +189,8 @@ architecture eth of top_hwitl is
ip_address => (x"C0", x"A8", x"02", x"02")
);
signal rst : std_logic;
signal clk_phy : std_logic;
signal phy_pll_lock : std_logic;
signal rst : std_logic;
signal clk_phy : std_logic;
signal phy_out : phy_out_t;
signal phy_in : phy_in_t;
@ -230,6 +228,13 @@ begin
ethernet_ii_in => ethernet_ii_in(PROT_ARP)
);
ethernet_i_in <= ethernet_i_in_t'(
tx_mac_address => (others => (others => '-')),
tx_data => (others => '-'),
tx_en => '0',
tx_length => (others => '-')
);
trashernet_eth_inst : entity trashernet.trashernet_eth
generic map(
ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
@ -260,7 +265,7 @@ begin
port map(
CLK => clk,
CLKOP => clk_phy,
LOCK => phy_pll_lock
LOCK => open
);
trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc

View File

@ -155,7 +155,7 @@ begin
constant SR_ADDRESSES_OFFSET : integer := -8;
alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET);
alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET);
alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET);
alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC
alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET);
type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE);
@ -240,7 +240,7 @@ begin
state <= HEAD;
end if;
when IGNORE =>
when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err)
null;
end case;
end if;

View File

@ -102,7 +102,7 @@ begin
byte_count <= byte_count + 1;
end if;
end if;
when PAYLOAD =>
when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error)
if phy_out.rx_data_valid then
sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
if byte_count = CRC_LENGTH then

View File

@ -47,6 +47,8 @@ architecture rtl of trashernet_phy_cdc is
signal rx_data_valid_i : std_logic;
begin
assert F_CLK_PHY > 2 * F_CLK report "F_CLK_PHY must be at least 2x F_CLK" severity failure;
-- -------------------------------------------------------------------------
-- Drives: PHY clock domain
-- -------------------------------------------------------------------------

View File

@ -82,7 +82,7 @@ package trashernet_pkg is
ethertype : ethertype_t;
end record;
type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- NULL range
constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic
constant ETHERNET_II_PROTOCOL_IP : ethernet_ii_protocol_t := (ethertype => (x"08", x"00"));
constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06"));