Fix linter warnings
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8d9ca9e784
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@ -26,9 +26,9 @@ entity top_hwitl is
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rx_p : in std_logic;
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rx_p : in std_logic;
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tx_p : out std_logic;
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tx_p : out std_logic;
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tx_n : out std_logic;
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tx_n : out std_logic;
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led_n : out std_logic_vector(7 downto 0);
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led_n : out std_logic_vector(7 downto 0); -- @suppress: Used in different architectures
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button_n : in std_logic_vector(3 downto 0);
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button_n : in std_logic_vector(3 downto 0); -- @suppress: Used in different architectures
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debug_data : out std_logic_vector(7 downto 0)
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debug_data : out std_logic_vector(7 downto 0) -- @suppress: Used in different architectures
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);
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);
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end entity top_hwitl;
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end entity top_hwitl;
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@ -50,7 +50,6 @@ architecture mac of top_hwitl is
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signal rst : std_logic;
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signal rst : std_logic;
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signal clk_phy : std_logic;
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signal clk_phy : std_logic;
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signal phy_pll_lock : std_logic;
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signal phy_out : phy_out_t;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal phy_in : phy_in_t;
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@ -80,7 +79,7 @@ begin
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port map(
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port map(
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CLK => clk,
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CLK => clk,
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CLKOP => clk_phy,
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CLKOP => clk_phy,
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LOCK => phy_pll_lock
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LOCK => open
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);
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);
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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@ -192,7 +191,6 @@ architecture eth of top_hwitl is
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signal rst : std_logic;
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signal rst : std_logic;
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signal clk_phy : std_logic;
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signal clk_phy : std_logic;
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signal phy_pll_lock : std_logic;
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signal phy_out : phy_out_t;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal phy_in : phy_in_t;
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@ -230,6 +228,13 @@ begin
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ethernet_ii_in => ethernet_ii_in(PROT_ARP)
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ethernet_ii_in => ethernet_ii_in(PROT_ARP)
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);
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);
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ethernet_i_in <= ethernet_i_in_t'(
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tx_mac_address => (others => (others => '-')),
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tx_data => (others => '-'),
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tx_en => '0',
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tx_length => (others => '-')
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);
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trashernet_eth_inst : entity trashernet.trashernet_eth
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trashernet_eth_inst : entity trashernet.trashernet_eth
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generic map(
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generic map(
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ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
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ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
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@ -260,7 +265,7 @@ begin
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port map(
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port map(
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CLK => clk,
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CLK => clk,
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CLKOP => clk_phy,
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CLKOP => clk_phy,
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LOCK => phy_pll_lock
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LOCK => open
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);
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);
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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@ -155,7 +155,7 @@ begin
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constant SR_ADDRESSES_OFFSET : integer := -8;
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constant SR_ADDRESSES_OFFSET : integer := -8;
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alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC
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alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET);
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alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET);
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type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE);
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type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE);
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@ -240,7 +240,7 @@ begin
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state <= HEAD;
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state <= HEAD;
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end if;
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end if;
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when IGNORE =>
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when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err)
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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@ -102,7 +102,7 @@ begin
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byte_count <= byte_count + 1;
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byte_count <= byte_count + 1;
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end if;
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end if;
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end if;
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end if;
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when PAYLOAD =>
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when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error)
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if phy_out.rx_data_valid then
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if phy_out.rx_data_valid then
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sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
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sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
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if byte_count = CRC_LENGTH then
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if byte_count = CRC_LENGTH then
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@ -47,6 +47,8 @@ architecture rtl of trashernet_phy_cdc is
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signal rx_data_valid_i : std_logic;
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signal rx_data_valid_i : std_logic;
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begin
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begin
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assert F_CLK_PHY > 2 * F_CLK report "F_CLK_PHY must be at least 2x F_CLK" severity failure;
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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-- Drives: PHY clock domain
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-- Drives: PHY clock domain
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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@ -82,7 +82,7 @@ package trashernet_pkg is
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ethertype : ethertype_t;
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ethertype : ethertype_t;
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end record;
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end record;
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type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
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type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
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constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- NULL range
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constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic
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constant ETHERNET_II_PROTOCOL_IP : ethernet_ii_protocol_t := (ethertype => (x"08", x"00"));
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constant ETHERNET_II_PROTOCOL_IP : ethernet_ii_protocol_t := (ethertype => (x"08", x"00"));
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constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06"));
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constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06"));
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