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mac: Use records for header fields

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This commit is contained in:
Markus Koch 2021-09-25 11:20:26 +02:00
parent 9addd97b57
commit cf6fb61195
3 changed files with 70 additions and 76 deletions
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80
bench/bench_trashernet_mac.vhd
View File

@ -32,26 +32,22 @@ architecture bench of bench_trashernet_mac is
signal tx_data_en : std_logic; signal tx_data_en : std_logic;
signal tx_data_ack : std_logic; signal tx_data_ack : std_logic;
signal tx_active : std_logic; signal tx_active : std_logic;
signal tx_header : mac_header_fields;
signal carrier_detect : std_logic; signal carrier_detect : std_logic;
signal rx_error : std_logic; signal rx_error : std_logic;
signal rx_p : std_logic; signal rx_p : std_logic;
signal tx_p : std_logic; signal tx_p : std_logic;
signal tx_n : std_logic; signal tx_n : std_logic;
signal rx_mac_destination : mac_addr_t; signal rx_mac_data : byte;
signal rx_mac_source : mac_addr_t; signal rx_mac_valid : std_logic;
signal rx_mac_ethertype : ethertype_t; signal rx_mac_crc_ok : std_logic;
signal rx_mac_data : byte; signal rx_mac_crc_error : std_logic;
signal rx_mac_valid : std_logic; signal rx_mac_header_rcv : std_logic;
signal rx_mac_crc_ok : std_logic; signal tx_mac_data : byte;
signal rx_mac_crc_error : std_logic; signal tx_mac_data_en : std_logic;
signal rx_mac_header_rcv : std_logic; signal tx_mac_data_ack : std_logic;
signal tx_mac_destination : mac_addr_t; signal rx_header : mac_header_fields;
signal tx_mac_source : mac_addr_t;
signal tx_mac_ethertype : ethertype_t;
signal tx_mac_data : byte;
signal tx_mac_data_en : std_logic;
signal tx_mac_data_ack : std_logic;
constant TEST_BENCH_LOOPBACK : boolean := true; constant TEST_BENCH_LOOPBACK : boolean := true;
@ -81,31 +77,27 @@ begin
trashernet_mac_inst : entity trashernet.trashernet_mac trashernet_mac_inst : entity trashernet.trashernet_mac
port map( port map(
clk => clk, clk => clk,
rst => rst, rst => rst,
rx_data => rx_data, rx_data => rx_data,
rx_data_valid => rx_data_valid, rx_data_valid => rx_data_valid,
rx_active => rx_active, rx_active => rx_active,
tx_data => tx_data, tx_data => tx_data,
tx_data_en => tx_data_en, tx_data_en => tx_data_en,
tx_data_ack => tx_data_ack, tx_data_ack => tx_data_ack,
tx_active => tx_active, tx_active => tx_active,
carrier_detect => carrier_detect, carrier_detect => carrier_detect,
rx_error => rx_error, rx_error => rx_error,
rx_mac_destination => rx_mac_destination, rx_header => rx_header,
rx_mac_source => rx_mac_source, rx_mac_data => rx_mac_data,
rx_mac_ethertype => rx_mac_ethertype, rx_mac_valid => rx_mac_valid,
rx_mac_data => rx_mac_data, rx_mac_header_rcv => rx_mac_header_rcv,
rx_mac_valid => rx_mac_valid, rx_mac_crc_ok => rx_mac_crc_ok,
rx_mac_header_rcv => rx_mac_header_rcv, rx_mac_crc_error => rx_mac_crc_error,
rx_mac_crc_ok => rx_mac_crc_ok, tx_header => tx_header,
rx_mac_crc_error => rx_mac_crc_error, tx_mac_data => tx_mac_data,
tx_mac_destination => tx_mac_destination, tx_mac_data_en => tx_mac_data_en,
tx_mac_source => tx_mac_source, tx_mac_data_ack => tx_mac_data_ack
tx_mac_ethertype => tx_mac_ethertype,
tx_mac_data => tx_mac_data,
tx_mac_data_en => tx_mac_data_en,
tx_mac_data_ack => tx_mac_data_ack
); );
clock_driver : process clock_driver : process
@ -188,11 +180,11 @@ begin
mac_tx : process is mac_tx : process is
begin begin
tx_mac_data <= x"11"; tx_mac_data <= x"11";
tx_mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67"); tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
tx_mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7"); tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
tx_mac_ethertype <= (x"01", x"00"); tx_header.mac_ethertype <= (x"01", x"00");
tx_mac_data_en <= '0'; tx_mac_data_en <= '0';
wait until rst = '0'; wait until rst = '0';
wait for 100 ns; wait for 100 ns;

60
trashernet/trashernet_mac.vhd
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@ -18,38 +18,34 @@ use work.trashernet_pkg.all;
entity trashernet_mac is entity trashernet_mac is
port( port(
-- Global -- Global
clk : in std_logic; -- Global clock clk : in std_logic; -- Global clock
rst : in std_logic; -- Asynchronous reset rst : in std_logic; -- Asynchronous reset
-- PHY signals -- PHY signals
rx_data : in byte; -- RX Data rx_data : in byte; -- RX Data
rx_data_valid : in std_logic; -- RX Data valid rx_data_valid : in std_logic; -- RX Data valid
rx_active : in std_logic; -- RX of packet in progress rx_active : in std_logic; -- RX of packet in progress
tx_data : out byte; -- TX Data tx_data : out byte; -- TX Data
tx_data_en : out std_logic; -- Transmitter enable tx_data_en : out std_logic; -- Transmitter enable
tx_data_ack : in std_logic; -- Latched data_tx tx_data_ack : in std_logic; -- Latched data_tx
tx_active : in std_logic; -- Transmitter active tx_active : in std_logic; -- Transmitter active
carrier_detect : in std_logic; -- Carrier detected carrier_detect : in std_logic; -- Carrier detected
rx_error : in std_logic; -- Receive error rx_error : in std_logic; -- Receive error
-- MAC signals -- MAC signals
rx_mac_destination : out mac_addr_t; -- Destination MAC address rx_header : out mac_header_fields; -- RX MAC Header Data
rx_mac_source : out mac_addr_t; -- Source MAC address rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid
rx_mac_ethertype : out ethertype_t; -- Ethertype or length rx_mac_data : out byte; -- Ethernet data (after Ethertype)
rx_mac_data : out byte; -- Ethernet data (after Ethertype) rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid
rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid
rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid
tx_mac_destination : in mac_addr_t; -- Destination MAC address tx_header : in mac_header_fields; -- TX MAC Header Data
tx_mac_source : in mac_addr_t; -- Source MAC address tx_mac_data : in byte; -- Payload
tx_mac_ethertype : in ethertype_t; -- Ethertype or length tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame
tx_mac_data : in byte; -- Payload tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word.
tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame
tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word.
); );
end entity trashernet_mac; end entity trashernet_mac;
@ -60,7 +56,7 @@ begin
rx : block rx : block
type state_t is (HEAD, PAYLOAD); type state_t is (HEAD, PAYLOAD);
constant HEAD_LENGTH : integer := rx_mac_destination'length + rx_mac_source'length + rx_mac_ethertype'length; constant HEAD_LENGTH : integer := rx_header.mac_destination'length + rx_header.mac_source'length + rx_header.mac_ethertype'length;
constant CRC_LENGTH : integer := 4; constant CRC_LENGTH : integer := 4;
signal state : state_t; signal state : state_t;
signal sr_head : byte_vector(0 to HEAD_LENGTH - 1); signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
@ -148,10 +144,10 @@ begin
end if; end if;
end process main; end process main;
rx_mac_destination <= sr_head(0 to 5); rx_header.mac_destination <= sr_head(0 to 5);
rx_mac_source <= sr_head(6 to 11); rx_header.mac_source <= sr_head(6 to 11);
rx_mac_ethertype <= sr_head(12 to 13); rx_header.mac_ethertype <= sr_head(12 to 13);
rx_mac_data <= sr_payload(0); rx_mac_data <= sr_payload(0);
end block rx; end block rx;
@ -159,7 +155,7 @@ begin
type tx_state_t is (IDLE, HEADER, DATA, TXCRC); type tx_state_t is (IDLE, HEADER, DATA, TXCRC);
signal tx_state : tx_state_t; signal tx_state : tx_state_t;
signal sr : byte_vector(0 to tx_mac_destination'length + tx_mac_source'length + tx_mac_ethertype'length - 1); signal sr : byte_vector(0 to tx_header.mac_destination'length + tx_header.mac_source'length + tx_header.mac_ethertype'length - 1);
constant BIT_CNT_MAX : integer := sr'high; constant BIT_CNT_MAX : integer := sr'high;
signal byte_cnt : integer range 0 to BIT_CNT_MAX; signal byte_cnt : integer range 0 to BIT_CNT_MAX;
@ -209,7 +205,7 @@ begin
when HEADER => when HEADER =>
if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
sr <= tx_mac_destination & tx_mac_source & tx_mac_ethertype; sr <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype;
crc_valid <= '1'; crc_valid <= '1';
byte_cnt <= BIT_CNT_MAX; byte_cnt <= BIT_CNT_MAX;
tx_state <= DATA; tx_state <= DATA;

6
trashernet/trashernet_pkg.vhd
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@ -17,6 +17,12 @@ package trashernet_pkg is
subtype mac_addr_t is byte_vector(0 to 5); subtype mac_addr_t is byte_vector(0 to 5);
subtype ip_addr_t is byte_vector(0 to 3); subtype ip_addr_t is byte_vector(0 to 3);
subtype ethertype_t is byte_vector(0 to 1); subtype ethertype_t is byte_vector(0 to 1);
type mac_header_fields is record
mac_destination : mac_addr_t; -- Destination MAC address
mac_source : mac_addr_t; -- Source MAC address
mac_ethertype : ethertype_t; -- Ethertype or length
end record mac_header_fields;
end package trashernet_pkg; end package trashernet_pkg;
package body trashernet_pkg is package body trashernet_pkg is