mac: Use records for header fields
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@ -32,26 +32,22 @@ architecture bench of bench_trashernet_mac is
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signal tx_data_en : std_logic;
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signal tx_data_ack : std_logic;
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signal tx_active : std_logic;
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signal tx_header : mac_header_fields;
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signal carrier_detect : std_logic;
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signal rx_error : std_logic;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal rx_mac_destination : mac_addr_t;
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signal rx_mac_source : mac_addr_t;
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signal rx_mac_ethertype : ethertype_t;
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signal rx_mac_data : byte;
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signal rx_mac_valid : std_logic;
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signal rx_mac_crc_ok : std_logic;
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signal rx_mac_crc_error : std_logic;
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signal rx_mac_header_rcv : std_logic;
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signal tx_mac_destination : mac_addr_t;
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signal tx_mac_source : mac_addr_t;
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signal tx_mac_ethertype : ethertype_t;
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signal tx_mac_data : byte;
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signal tx_mac_data_en : std_logic;
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signal tx_mac_data_ack : std_logic;
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signal rx_header : mac_header_fields;
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constant TEST_BENCH_LOOPBACK : boolean := true;
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@ -92,17 +88,13 @@ begin
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tx_active => tx_active,
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carrier_detect => carrier_detect,
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rx_error => rx_error,
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rx_mac_destination => rx_mac_destination,
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rx_mac_source => rx_mac_source,
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rx_mac_ethertype => rx_mac_ethertype,
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rx_header => rx_header,
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rx_mac_data => rx_mac_data,
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rx_mac_valid => rx_mac_valid,
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rx_mac_header_rcv => rx_mac_header_rcv,
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rx_mac_crc_ok => rx_mac_crc_ok,
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rx_mac_crc_error => rx_mac_crc_error,
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tx_mac_destination => tx_mac_destination,
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tx_mac_source => tx_mac_source,
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tx_mac_ethertype => tx_mac_ethertype,
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tx_header => tx_header,
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tx_mac_data => tx_mac_data,
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tx_mac_data_en => tx_mac_data_en,
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tx_mac_data_ack => tx_mac_data_ack
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@ -189,9 +181,9 @@ begin
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mac_tx : process is
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begin
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tx_mac_data <= x"11";
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tx_mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
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tx_mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
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tx_mac_ethertype <= (x"01", x"00");
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tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
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tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
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tx_header.mac_ethertype <= (x"01", x"00");
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tx_mac_data_en <= '0';
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wait until rst = '0';
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@ -35,18 +35,14 @@ entity trashernet_mac is
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rx_error : in std_logic; -- Receive error
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-- MAC signals
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rx_mac_destination : out mac_addr_t; -- Destination MAC address
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rx_mac_source : out mac_addr_t; -- Source MAC address
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rx_mac_ethertype : out ethertype_t; -- Ethertype or length
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rx_header : out mac_header_fields; -- RX MAC Header Data
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rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid
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rx_mac_data : out byte; -- Ethernet data (after Ethertype)
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rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid
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rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid
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rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
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rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid
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tx_mac_destination : in mac_addr_t; -- Destination MAC address
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tx_mac_source : in mac_addr_t; -- Source MAC address
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tx_mac_ethertype : in ethertype_t; -- Ethertype or length
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tx_header : in mac_header_fields; -- TX MAC Header Data
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tx_mac_data : in byte; -- Payload
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tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame
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tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word.
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@ -60,7 +56,7 @@ begin
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rx : block
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type state_t is (HEAD, PAYLOAD);
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constant HEAD_LENGTH : integer := rx_mac_destination'length + rx_mac_source'length + rx_mac_ethertype'length;
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constant HEAD_LENGTH : integer := rx_header.mac_destination'length + rx_header.mac_source'length + rx_header.mac_ethertype'length;
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constant CRC_LENGTH : integer := 4;
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signal state : state_t;
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signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
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@ -148,9 +144,9 @@ begin
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end if;
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end process main;
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rx_mac_destination <= sr_head(0 to 5);
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rx_mac_source <= sr_head(6 to 11);
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rx_mac_ethertype <= sr_head(12 to 13);
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rx_header.mac_destination <= sr_head(0 to 5);
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rx_header.mac_source <= sr_head(6 to 11);
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rx_header.mac_ethertype <= sr_head(12 to 13);
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rx_mac_data <= sr_payload(0);
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end block rx;
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@ -159,7 +155,7 @@ begin
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type tx_state_t is (IDLE, HEADER, DATA, TXCRC);
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signal tx_state : tx_state_t;
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signal sr : byte_vector(0 to tx_mac_destination'length + tx_mac_source'length + tx_mac_ethertype'length - 1);
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signal sr : byte_vector(0 to tx_header.mac_destination'length + tx_header.mac_source'length + tx_header.mac_ethertype'length - 1);
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constant BIT_CNT_MAX : integer := sr'high;
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signal byte_cnt : integer range 0 to BIT_CNT_MAX;
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@ -209,7 +205,7 @@ begin
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when HEADER =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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sr <= tx_mac_destination & tx_mac_source & tx_mac_ethertype;
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sr <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype;
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crc_valid <= '1';
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byte_cnt <= BIT_CNT_MAX;
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tx_state <= DATA;
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@ -17,6 +17,12 @@ package trashernet_pkg is
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subtype mac_addr_t is byte_vector(0 to 5);
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subtype ip_addr_t is byte_vector(0 to 3);
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subtype ethertype_t is byte_vector(0 to 1);
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type mac_header_fields is record
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mac_destination : mac_addr_t; -- Destination MAC address
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mac_source : mac_addr_t; -- Source MAC address
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mac_ethertype : ethertype_t; -- Ethertype or length
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end record mac_header_fields;
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end package trashernet_pkg;
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package body trashernet_pkg is
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