phy: Refactor to use records for the application interface
This commit is contained in:
parent
cf6fb61195
commit
cfac94136a
@ -22,22 +22,15 @@ entity bench_trashernet_mac is
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end entity bench_trashernet_mac;
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architecture bench of bench_trashernet_mac is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_data_valid : std_logic;
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signal rx_active : std_logic;
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signal tx_data : std_logic_vector(7 downto 0);
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signal tx_data_en : std_logic;
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signal tx_data_ack : std_logic;
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signal tx_active : std_logic;
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signal tx_header : mac_header_fields;
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signal carrier_detect : std_logic;
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signal rx_error : std_logic;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal rx_mac_data : byte;
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signal rx_mac_valid : std_logic;
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@ -48,6 +41,7 @@ architecture bench of bench_trashernet_mac is
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signal tx_mac_data_en : std_logic;
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signal tx_mac_data_ack : std_logic;
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signal rx_header : mac_header_fields;
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signal tx_header : mac_header_fields;
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constant TEST_BENCH_LOOPBACK : boolean := true;
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@ -58,40 +52,26 @@ begin
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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rx_data => rx_data,
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rx_data_valid => rx_data_valid,
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rx_active => rx_active,
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tx_data => tx_data,
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tx_data_en => tx_data_en,
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tx_data_ack => tx_data_ack,
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tx_active => tx_active,
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carrier_detect => carrier_detect,
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rx_error => rx_error,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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clk => clk,
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rst => rst,
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rx_data => rx_data,
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rx_data_valid => rx_data_valid,
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rx_active => rx_active,
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tx_data => tx_data,
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tx_data_en => tx_data_en,
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tx_data_ack => tx_data_ack,
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tx_active => tx_active,
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carrier_detect => carrier_detect,
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rx_error => rx_error,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_header => rx_header,
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rx_mac_header_rcv => rx_mac_header_rcv,
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rx_mac_data => rx_mac_data,
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rx_mac_valid => rx_mac_valid,
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rx_mac_header_rcv => rx_mac_header_rcv,
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rx_mac_crc_ok => rx_mac_crc_ok,
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rx_mac_crc_error => rx_mac_crc_error,
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tx_header => tx_header,
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@ -164,8 +144,8 @@ begin
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receiver : process is
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begin
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wait until rising_edge(clk);
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if rx_data_valid then
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report "[PHY] RX byte: " & to_hstring(rx_data);
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if phy_out.rx_data_valid then
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report "[PHY] RX byte: " & to_hstring(phy_out.rx_data);
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end if;
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if rx_mac_valid then
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report "[MAC] RX byte: " & to_hstring(rx_mac_data);
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@ -25,18 +25,12 @@ architecture bench of bench_trashernet_phy is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_data_valid : std_logic;
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signal rx_active : std_logic;
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signal tx_data : std_logic_vector(7 downto 0);
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signal tx_data_en : std_logic;
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signal tx_data_ack : std_logic;
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signal carrier_detect : std_logic;
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signal rx_error : std_logic;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_active : std_logic;
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signal tx_n : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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begin
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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@ -45,21 +39,14 @@ begin
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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rx_data => rx_data,
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rx_data_valid => rx_data_valid,
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rx_active => rx_active,
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tx_data => tx_data,
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tx_data_en => tx_data_en,
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tx_data_ack => tx_data_ack,
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tx_active => tx_active,
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carrier_detect => carrier_detect,
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rx_error => rx_error,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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clock_driver : process
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@ -96,8 +83,8 @@ begin
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receiver : process is
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begin
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wait until rising_edge(clk);
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if rx_data_valid then
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report "RX byte: " & to_hstring(rx_data);
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if phy_out.rx_data_valid then
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report "RX byte: " & to_hstring(phy_out.rx_data);
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end if;
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end process receiver;
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@ -22,17 +22,8 @@ entity trashernet_mac is
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rst : in std_logic; -- Asynchronous reset
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-- PHY signals
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rx_data : in byte; -- RX Data
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rx_data_valid : in std_logic; -- RX Data valid
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rx_active : in std_logic; -- RX of packet in progress
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tx_data : out byte; -- TX Data
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tx_data_en : out std_logic; -- Transmitter enable
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tx_data_ack : in std_logic; -- Latched data_tx
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tx_active : in std_logic; -- Transmitter active
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carrier_detect : in std_logic; -- Carrier detected
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rx_error : in std_logic; -- Receive error
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phy_out : in phy_out_t; -- PHY application IF (out of PHY)
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phy_in : out phy_in_t; -- PHY application IF (into PHY)
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-- MAC signals
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rx_header : out mac_header_fields; -- RX MAC Header Data
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@ -79,8 +70,8 @@ begin
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port map(
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clk => clk,
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rst => rst,
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data => rx_data,
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data_valid => rx_data_valid,
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data => phy_out.rx_data,
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data_valid => phy_out.rx_data_valid,
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crc_clear => crc_clear,
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crc_out => crc
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);
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@ -106,8 +97,8 @@ begin
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case state is
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when HEAD =>
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if rx_data_valid then
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sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & rx_data;
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if phy_out.rx_data_valid then
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sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & phy_out.rx_data;
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if byte_count = (HEAD_LENGTH - 1) then
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state <= PAYLOAD;
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byte_count <= 0;
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@ -119,24 +110,24 @@ begin
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end if;
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end if;
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when PAYLOAD =>
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if rx_data_valid then
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sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & rx_data;
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if phy_out.rx_data_valid then
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sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
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if byte_count = CRC_LENGTH then
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rx_mac_valid <= '1';
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else
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byte_count <= byte_count + 1;
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end if;
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end if;
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if not rx_active then
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if not phy_out.rx_active then
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rx_mac_crc_ok <= crc_ok;
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rx_mac_crc_error <= not crc_ok;
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end if;
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if rx_error then
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if phy_out.rx_error then
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rx_mac_crc_error <= '1';
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end if;
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end case;
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if (not rx_active) or rx_error then
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if (not phy_out.rx_active) or phy_out.rx_error then
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byte_count <= 0;
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state <= HEAD;
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crc_clear <= '1';
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@ -173,7 +164,7 @@ begin
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port map(
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clk => clk,
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rst => rst,
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data => tx_data,
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data => phy_in.tx_data,
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data_valid => crc_valid,
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crc_clear => crc_clear,
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crc_out => crc
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@ -188,7 +179,7 @@ begin
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tx_mac_data_ack <= '0';
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crc_valid <= '0';
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if tx_data_ack then
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if phy_out.tx_data_ack then
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sr <= sr(sr'low + 1 to sr'high) & x"00";
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crc_valid <= '1';
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if byte_cnt /= 0 then
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@ -197,14 +188,14 @@ begin
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end if;
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case tx_state is
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when IDLE =>
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if not tx_active and tx_mac_data_en then
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if not phy_out.tx_active and tx_mac_data_en then
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sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
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byte_cnt <= 7;
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tx_state <= HEADER;
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end if;
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when HEADER =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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sr <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype;
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crc_valid <= '1';
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byte_cnt <= BIT_CNT_MAX;
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@ -212,7 +203,7 @@ begin
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end if;
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when DATA =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
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if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
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if tx_mac_data_en then
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sr(0) <= tx_mac_data;
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tx_mac_data_ack <= '1';
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@ -224,15 +215,15 @@ begin
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end if;
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when TXCRC =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete
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if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete
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tx_state <= IDLE;
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end if;
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end case;
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end if;
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end process tx_main;
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tx_data_en <= '1' when tx_state /= IDLE else '0';
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crc_clear <= '1' when tx_state = HEADER else '0';
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tx_data <= sr(sr'low);
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phy_in.tx_data_en <= '1' when tx_state /= IDLE else '0';
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crc_clear <= '1' when tx_state = HEADER else '0';
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phy_in.tx_data <= sr(sr'low);
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end block tx;
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end architecture rtl;
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@ -22,26 +22,17 @@ entity trashernet_phy is
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);
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- Eth
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rx_data : out byte; -- RX Data
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rx_data_valid : out std_logic; -- RX Data valid
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rx_active : out std_logic; -- RX of packet in progress
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tx_data : in byte; -- TX Data
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tx_data_en : in std_logic; -- Transmitter enable
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tx_data_ack : out std_logic; -- Latched data_tx
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tx_active : out std_logic; -- Transmission in progress
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carrier_detect : out std_logic; -- Carrier detected
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rx_error : out std_logic; -- Receive error
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-- PHY application interface
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phy_out : out phy_out_t; -- PHY application IF (out)
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phy_in : in phy_in_t; -- PHY application IF (in)
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-- Ethernet physical signals
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rx_p : in std_logic;
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tx_p : out std_logic;
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tx_n : out std_logic
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rx_p : in std_logic;
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tx_p : out std_logic;
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tx_n : out std_logic
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);
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end entity trashernet_phy;
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@ -69,7 +60,7 @@ begin
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signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX;
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begin
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-- Synchronize RX input
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synchronizer_inst : entity work.synchronizer
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synchronizer_rxp_inst : entity work.synchronizer
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port map(
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clk => clk,
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rst => rst,
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@ -188,11 +179,11 @@ begin
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if rst then
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demanchestization_state <= SYNC;
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bit_stb <= '0';
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rx_active <= '0';
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rx_error <= '0';
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phy_out.rx_active <= '0';
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phy_out.rx_error <= '0';
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elsif rising_edge(clk) then
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bit_stb <= '0';
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rx_error <= '0';
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bit_stb <= '0';
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phy_out.rx_error <= '0';
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if (bit_ev /= NONE) then
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case demanchestization_state is
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@ -200,7 +191,7 @@ begin
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if (bit_ev = KEEP) then
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bit_value <= '1';
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demanchestization_state <= DATA;
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rx_active <= '1';
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phy_out.rx_active <= '1';
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end if;
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when DATA => -- @suppress: Condition outside of case allows to exit this state
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bit_value <= not bit_value when bit_ev = TOGGLE else bit_value;
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@ -211,13 +202,13 @@ begin
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end if;
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if (bit_ev = ERROR) then
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rx_error <= '1';
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phy_out.rx_error <= '1';
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demanchestization_state <= ERROR;
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end if;
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if (not transition_activity) then
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demanchestization_state <= SYNC;
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rx_active <= '0';
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phy_out.rx_active <= '0';
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end if;
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end if;
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end process bit_recovery;
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@ -227,17 +218,17 @@ begin
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bytizer : process(clk, rst) is
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begin
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if rst then
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rx_data_valid <= '0';
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phy_out.rx_data_valid <= '0';
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elsif rising_edge(clk) then
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rx_data_valid <= '0';
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phy_out.rx_data_valid <= '0';
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if rx_active then
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if phy_out.rx_active then
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if (bit_stb) then
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rx_data <= bit_value & rx_data(rx_data'high downto rx_data'low + 1);
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phy_out.rx_data <= bit_value & phy_out.rx_data(phy_out.rx_data'high downto phy_out.rx_data'low + 1);
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if (bit_cnt = 7) then
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rx_data_valid <= '1';
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bit_cnt <= 0;
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phy_out.rx_data_valid <= '1';
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bit_cnt <= 0;
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else
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bit_cnt <= bit_cnt + 1;
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end if;
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@ -263,7 +254,7 @@ begin
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end if;
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end if;
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end process nlp_timeout_p;
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carrier_detect <= '1' when nlp_timeout_cnt /= 0 else '0';
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phy_out.carrier_detect <= '1' when nlp_timeout_cnt /= 0 else '0';
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end block receiver;
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-- -------------------------------------------------------------------------
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@ -274,7 +265,7 @@ begin
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type tx_state_t is (IDLE, NLP, TX, IPG);
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signal tx_state : tx_state_t;
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signal sr : std_logic_vector(tx_data'range);
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signal sr : std_logic_vector(phy_in.tx_data'range);
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signal bit_stage : std_logic;
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constant BIT_CNT_MAX_NLP : integer := 16000 / 100; -- 16 ms (timebase 100 ns)
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@ -291,10 +282,10 @@ begin
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tx_state <= TX;
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tx_mode <= ACTIVE;
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sr <= tx_data;
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bit_stage <= '0';
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bit_cnt <= BIT_CNT_MAX_DATA;
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tx_data_ack <= '1';
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sr <= phy_in.tx_data;
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bit_stage <= '0';
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bit_cnt <= BIT_CNT_MAX_DATA;
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phy_out.tx_data_ack <= '1';
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end procedure transmit_byte;
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procedure transmit_ipg is
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@ -325,13 +316,13 @@ begin
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begin
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if rst then
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tx_data_ack <= '0';
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tx_stb_cnt <= TX_STB_CNT_MAX;
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tx_mode <= OFF;
|
||||
phy_out.tx_data_ack <= '0';
|
||||
tx_stb_cnt <= TX_STB_CNT_MAX;
|
||||
tx_mode <= OFF;
|
||||
go_idle;
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
tx_data_ack <= '0';
|
||||
phy_out.tx_data_ack <= '0';
|
||||
|
||||
if tx_stb_cnt = 0 then
|
||||
tx_stb_cnt <= TX_STB_CNT_MAX;
|
||||
@ -351,7 +342,7 @@ begin
|
||||
|
||||
case tx_state is
|
||||
when IDLE =>
|
||||
if tx_data_en then -- New packet to TX
|
||||
if phy_in.tx_data_en then -- New packet to TX
|
||||
transmit_byte;
|
||||
bit_stage <= '1';
|
||||
tx_stb_cnt <= TX_STB_CNT_MAX; -- resync
|
||||
@ -372,7 +363,7 @@ begin
|
||||
if (bit_stage = '1') then
|
||||
sr <= '0' & sr(sr'high downto sr'low + 1);
|
||||
if bit_cnt = 0 then
|
||||
if tx_data_en then
|
||||
if phy_in.tx_data_en then
|
||||
transmit_byte;
|
||||
else
|
||||
transmit_ipg;
|
||||
@ -387,7 +378,7 @@ begin
|
||||
end case;
|
||||
end if;
|
||||
end process tx_main;
|
||||
tx_active <= '1' when tx_state /= IDLE else '0';
|
||||
phy_out.tx_active <= '1' when tx_state /= IDLE else '0';
|
||||
|
||||
driver : process(clk, rst) is
|
||||
begin
|
||||
|
||||
@ -22,42 +22,26 @@ entity trashernet_phy_cdc is
|
||||
);
|
||||
port(
|
||||
-- Global
|
||||
clk : in std_logic; -- Clock for internal interface
|
||||
phy_clk : in std_logic; -- Clock for PHY (rx_p, tx_p)
|
||||
rst : in std_logic; -- Asynchronous reset
|
||||
clk : in std_logic; -- Clock for internal interface
|
||||
phy_clk : in std_logic; -- Clock for PHY (rx_p, tx_p)
|
||||
rst : in std_logic; -- Asynchronous reset
|
||||
|
||||
-- System interface
|
||||
rx_data : out byte; -- RX Data
|
||||
rx_data_valid : out std_logic; -- RX Data valid
|
||||
rx_active : out std_logic; -- RX of packet in progress
|
||||
|
||||
tx_data : in byte; -- TX Data
|
||||
tx_data_en : in std_logic; -- Transmitter enable
|
||||
tx_data_ack : out std_logic; -- Latched data_tx
|
||||
tx_active : out std_logic; -- Transmission in progress
|
||||
|
||||
carrier_detect : out std_logic; -- Carrier detected
|
||||
rx_error : out std_logic; -- Receive error
|
||||
-- PHY application interface
|
||||
phy_out : out phy_out_t; -- PHY application IF (out)
|
||||
phy_in : in phy_in_t; -- PHY application IF (in)
|
||||
|
||||
-- Ethernet physical signals
|
||||
rx_p : in std_logic;
|
||||
tx_p : out std_logic;
|
||||
tx_n : out std_logic
|
||||
rx_p : in std_logic;
|
||||
tx_p : out std_logic;
|
||||
tx_n : out std_logic
|
||||
);
|
||||
end entity trashernet_phy_cdc;
|
||||
|
||||
architecture RTL of trashernet_phy_cdc is
|
||||
architecture rtl of trashernet_phy_cdc is
|
||||
-- PHY signals
|
||||
signal phy_rst : std_logic;
|
||||
signal phy_rx_data : std_logic_vector(7 downto 0);
|
||||
signal phy_rx_data_valid : std_logic;
|
||||
signal phy_rx_active : std_logic;
|
||||
signal phy_tx_data : std_logic_vector(7 downto 0);
|
||||
signal phy_tx_data_en : std_logic;
|
||||
signal phy_tx_data_ack : std_logic;
|
||||
signal phy_carrier_detect : std_logic;
|
||||
signal phy_rx_error : std_logic;
|
||||
signal phy_tx_active : std_logic;
|
||||
signal phy_rst : std_logic;
|
||||
signal phy_phy_out : phy_out_t;
|
||||
signal phy_phy_in : phy_in_t;
|
||||
|
||||
-- Helper signals
|
||||
signal rx_data_valid_i : std_logic;
|
||||
@ -80,20 +64,13 @@ begin
|
||||
F_CLK => F_CLK_PHY
|
||||
)
|
||||
port map(
|
||||
clk => phy_clk,
|
||||
rst => phy_rst,
|
||||
rx_data => phy_rx_data,
|
||||
rx_data_valid => phy_rx_data_valid,
|
||||
rx_active => phy_rx_active,
|
||||
tx_data => phy_tx_data,
|
||||
tx_data_en => phy_tx_data_en,
|
||||
tx_data_ack => phy_tx_data_ack,
|
||||
tx_active => phy_tx_active,
|
||||
carrier_detect => phy_carrier_detect,
|
||||
rx_error => phy_rx_error,
|
||||
rx_p => rx_p,
|
||||
tx_p => tx_p,
|
||||
tx_n => tx_n
|
||||
clk => phy_clk,
|
||||
rst => phy_rst,
|
||||
phy_out => phy_phy_out,
|
||||
phy_in => phy_phy_in,
|
||||
rx_p => rx_p,
|
||||
tx_p => tx_p,
|
||||
tx_n => tx_n
|
||||
);
|
||||
|
||||
synchronizer_txen_inst : entity work.synchronizer
|
||||
@ -103,11 +80,11 @@ begin
|
||||
port map(
|
||||
clk => phy_clk,
|
||||
rst => phy_rst,
|
||||
data_in => tx_data_en,
|
||||
data_out => phy_tx_data_en
|
||||
data_in => phy_in.tx_data_en,
|
||||
data_out => phy_phy_in.tx_data_en
|
||||
);
|
||||
|
||||
phy_tx_data <= tx_data; -- When tx_data_en is through the synchronizer, this should be stable (and in the other direction, it should only change when we don't read it anyways)
|
||||
phy_phy_in.tx_data <= phy_in.tx_data; -- When tx_data_en is through the synchronizer, this should be stable (and in the other direction, it should only change when we don't read it anyways)
|
||||
|
||||
-- -------------------------------------------------------------------------
|
||||
-- Drives: System clock domain
|
||||
@ -116,7 +93,7 @@ begin
|
||||
port map(
|
||||
a_clk => phy_clk,
|
||||
a_rst => phy_rst,
|
||||
a_in => phy_rx_data_valid,
|
||||
a_in => phy_phy_out.rx_data_valid,
|
||||
b_clk => clk,
|
||||
b_rst => rst,
|
||||
b_out => rx_data_valid_i
|
||||
@ -125,10 +102,10 @@ begin
|
||||
rxdvff : process(clk, rst) is
|
||||
begin
|
||||
if rst then
|
||||
rx_data_valid <= '0';
|
||||
phy_out.rx_data_valid <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
rx_data_valid <= rx_data_valid_i;
|
||||
rx_data <= phy_rx_data; -- Data should be stable after the time it takes the _valid signal to go through the synchronizer
|
||||
phy_out.rx_data_valid <= rx_data_valid_i;
|
||||
phy_out.rx_data <= phy_phy_out.rx_data; -- Data should be stable after the time it takes the _valid signal to go through the synchronizer
|
||||
end if;
|
||||
end process rxdvff;
|
||||
|
||||
@ -136,44 +113,44 @@ begin
|
||||
port map(
|
||||
a_clk => phy_clk,
|
||||
a_rst => phy_rst,
|
||||
a_in => phy_rx_error,
|
||||
a_in => phy_phy_out.rx_error,
|
||||
b_clk => clk,
|
||||
b_rst => rst,
|
||||
b_out => rx_error
|
||||
b_out => phy_out.rx_error
|
||||
);
|
||||
|
||||
synchronizer_rxa_inst : entity work.synchronizer
|
||||
port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
data_in => phy_rx_active,
|
||||
data_out => rx_active
|
||||
data_in => phy_phy_out.rx_active,
|
||||
data_out => phy_out.rx_active
|
||||
);
|
||||
|
||||
cdc_strobe_txack_inst : entity work.cdc_strobe
|
||||
port map(
|
||||
a_clk => phy_clk,
|
||||
a_rst => phy_rst,
|
||||
a_in => phy_tx_data_ack,
|
||||
a_in => phy_phy_out.tx_data_ack,
|
||||
b_clk => clk,
|
||||
b_rst => rst,
|
||||
b_out => tx_data_ack
|
||||
b_out => phy_out.tx_data_ack
|
||||
);
|
||||
|
||||
synchronizer_crs_inst : entity work.synchronizer
|
||||
port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
data_in => phy_carrier_detect,
|
||||
data_out => carrier_detect
|
||||
data_in => phy_phy_out.carrier_detect,
|
||||
data_out => phy_out.carrier_detect
|
||||
);
|
||||
|
||||
synchronizer_txa_inst : entity work.synchronizer
|
||||
port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
data_in => phy_tx_active,
|
||||
data_out => tx_active
|
||||
data_in => phy_phy_out.tx_active,
|
||||
data_out => phy_out.tx_active
|
||||
);
|
||||
|
||||
end architecture RTL;
|
||||
end architecture rtl;
|
||||
|
||||
@ -19,10 +19,27 @@ package trashernet_pkg is
|
||||
subtype ethertype_t is byte_vector(0 to 1);
|
||||
|
||||
type mac_header_fields is record
|
||||
mac_destination : mac_addr_t; -- Destination MAC address
|
||||
mac_source : mac_addr_t; -- Source MAC address
|
||||
mac_ethertype : ethertype_t; -- Ethertype or length
|
||||
mac_destination : mac_addr_t; -- Destination MAC address
|
||||
mac_source : mac_addr_t; -- Source MAC address
|
||||
mac_ethertype : ethertype_t; -- Ethertype or length
|
||||
end record mac_header_fields;
|
||||
|
||||
-- PHY interface
|
||||
type phy_in_t is record
|
||||
tx_data : byte; -- TX Data
|
||||
tx_data_en : std_logic; -- Transmitter enable
|
||||
end record phy_in_t;
|
||||
type phy_out_t is record
|
||||
rx_data : byte; -- RX Data
|
||||
rx_data_valid : std_logic; -- RX Data valid
|
||||
rx_active : std_logic; -- RX of packet in progress
|
||||
|
||||
tx_data_ack : std_logic; -- Latched data_tx
|
||||
tx_active : std_logic; -- Transmission in progress
|
||||
|
||||
carrier_detect : std_logic; -- Carrier detected
|
||||
rx_error : std_logic; -- Receive error
|
||||
end record phy_out_t;
|
||||
end package trashernet_pkg;
|
||||
|
||||
package body trashernet_pkg is
|
||||
|
||||
Loading…
Reference in New Issue
Block a user