demo: Add MAC demo design
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								demo/lattice_brevia2/.gitignore
									
									
									
									
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								demo/lattice_brevia2/.gitignore
									
									
									
									
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					impl1/
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					*.ccl
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					.recovery
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					.run_manager.ini
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					.setting.ini
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					.spread_sheet.ini
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					.spreadsheet_view.ini
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										112
									
								
								demo/lattice_brevia2/ip/pll0.vhd
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										112
									
								
								demo/lattice_brevia2/ip/pll0.vhd
									
									
									
									
									
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					-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2
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					-- Module  Version: 5.7
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					--/usr/local/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth lse -arch mg5a00 -type pll -fin 50 -phase_cntl STATIC -fclkop 140 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 
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					-- Sat Jan 22 20:39:11 2022
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					library IEEE;
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					use IEEE.std_logic_1164.all;
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					-- synopsys translate_off
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					library xp2;
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					use xp2.components.all;
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					-- synopsys translate_on
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					entity pll0 is
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						port(
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							CLK   : in  std_logic;
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							CLKOP : out std_logic;
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							LOCK  : out std_logic);
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					end pll0;
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					architecture Structure of pll0 is
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						-- internal signal declarations
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						signal CLKOP_t   : std_logic;
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						signal scuba_vlo : std_logic;
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						-- local component declarations
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						component VLO
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							port(Z : out std_logic);
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						end component;
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						component EPLLD1
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							-- synopsys translate_off
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							generic(CLKOK_BYPASS : in String; CLKOS_BYPASS : in String;
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							        CLKOP_BYPASS : in String; DUTY : in Integer;
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							        PHASEADJ     : in String; PHASE_CNTL : in String;
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							        CLKOK_DIV    : in Integer; CLKFB_DIV : in Integer;
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							        CLKOP_DIV    : in Integer; CLKI_DIV : in Integer);
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							-- synopsys translate_on
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							port(CLKI     : in  std_logic; CLKFB : in std_logic; RST : in std_logic;
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							     RSTK     : in  std_logic; DPAMODE : in std_logic; DRPAI3 : in std_logic;
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							     DRPAI2   : in  std_logic; DRPAI1 : in std_logic; DRPAI0 : in std_logic;
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							     DFPAI3   : in  std_logic; DFPAI2 : in std_logic; DFPAI1 : in std_logic;
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							     DFPAI0   : in  std_logic; PWD : in std_logic; CLKOP : out std_logic;
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							     CLKOS    : out std_logic; CLKOK : out std_logic; LOCK : out std_logic;
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							     CLKINTFB : out std_logic);
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						end component;
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						attribute CLKOK_BYPASS        : string;
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						attribute CLKOS_BYPASS        : string;
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						attribute FREQUENCY_PIN_CLKOP : string;
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						attribute CLKOP_BYPASS        : string;
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						attribute PHASE_CNTL          : string;
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						attribute DUTY                : string;
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						attribute PHASEADJ            : string;
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						attribute FREQUENCY_PIN_CLKI  : string;
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						attribute CLKOK_DIV           : string;
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						attribute CLKOP_DIV           : string;
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						attribute CLKFB_DIV           : string;
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						attribute CLKI_DIV            : string;
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						attribute FIN                 : string;
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						attribute CLKOK_BYPASS of PLLInst_0 : label is "DISABLED";
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						attribute CLKOS_BYPASS of PLLInst_0 : label is "DISABLED";
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						attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "140.000000";
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						attribute CLKOP_BYPASS of PLLInst_0 : label is "DISABLED";
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						attribute PHASE_CNTL of PLLInst_0 : label is "STATIC";
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						attribute DUTY of PLLInst_0 : label is "8";
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						attribute PHASEADJ of PLLInst_0 : label is "0.0";
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						attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "50.000000";
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						attribute CLKOK_DIV of PLLInst_0 : label is "2";
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						attribute CLKOP_DIV of PLLInst_0 : label is "4";
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						attribute CLKFB_DIV of PLLInst_0 : label is "14";
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						attribute CLKI_DIV of PLLInst_0 : label is "5";
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						attribute FIN of PLLInst_0 : label is "50.000000";
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						attribute syn_keep            : boolean;
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						attribute NGD_DRC_MASK        : integer;
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						attribute NGD_DRC_MASK of Structure : architecture is 1;
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					begin
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						-- component instantiation statements
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						scuba_vlo_inst : VLO
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							port map(Z => scuba_vlo);
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						PLLInst_0 : EPLLD1
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								-- synopsys translate_off
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							generic map(CLKOK_BYPASS => "DISABLED", CLKOS_BYPASS => "DISABLED",
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							            CLKOP_BYPASS => "DISABLED", PHASE_CNTL => "STATIC", DUTY => 8,
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							            PHASEADJ     => "0.0", CLKOK_DIV => 2, CLKOP_DIV => 4, CLKFB_DIV => 14,
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							            CLKI_DIV     => 5)
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								-- synopsys translate_on
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							port map(CLKI     => CLK, CLKFB => CLKOP_t, RST => scuba_vlo,
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							         RSTK     => scuba_vlo, DPAMODE => scuba_vlo, DRPAI3 => scuba_vlo,
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							         DRPAI2   => scuba_vlo, DRPAI1 => scuba_vlo, DRPAI0 => scuba_vlo,
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							         DFPAI3   => scuba_vlo, DFPAI2 => scuba_vlo, DFPAI1 => scuba_vlo,
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							         DFPAI0   => scuba_vlo, PWD => scuba_vlo, CLKOP => CLKOP_t,
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							         CLKOS    => open, CLKOK => open, LOCK => LOCK, CLKINTFB => open);
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						CLKOP <= CLKOP_t;
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					end Structure;
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					-- synopsys translate_off
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					library xp2;
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					configuration Structure_CON of pll0 is
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						for Structure
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							for all : VLO
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								use entity xp2.VLO(V);
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							end for;
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							for all : EPLLD1
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								use entity xp2.EPLLD1(V);
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							end for;
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						end for;
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					end Structure_CON;
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					-- synopsys translate_on
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										47
									
								
								demo/lattice_brevia2/mac_test/mac_test.ldf
									
									
									
									
									
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								demo/lattice_brevia2/mac_test/mac_test.ldf
									
									
									
									
									
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					<?xml version="1.0" encoding="UTF-8"?>
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					<BaliProject version="3.2" title="mac_test" device="LFXP2-5E-6TN144C" default_implementation="impl1">
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					    <Options/>
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					    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
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					        <Options def_top="trashernet.trashernet_eth" lib="work" top="top_mac_test"/>
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					        <Source name="../../design/top_mac_test.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="work" top_module="top_mac_test"/>
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					        </Source>
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					        <Source name="../../trashernet/cdc_strobe.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/crc.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/synchronizer.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/trashernet_eth.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/trashernet_mac.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/trashernet_phy.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/trashernet_phy_cdc.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../trashernet/trashernet_pkg.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="trashernet"/>
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					        </Source>
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					        <Source name="../../ip/pll0.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="work"/>
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					        </Source>
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					        <Source name="../../design/ledcon.vhd" type="VHDL" type_short="VHDL">
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					            <Options lib="work"/>
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					        </Source>
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					        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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					            <Options/>
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					        </Source>
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					        <Source name="mac_test.lpf" type="Logic Preference" type_short="LPF">
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					            <Options/>
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					        </Source>
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					    </Implementation>
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					    <Strategy name="Strategy1" file="mac_test1.sty"/>
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					</BaliProject>
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								demo/lattice_brevia2/mac_test/mac_test.lpf
									
									
									
									
									
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								demo/lattice_brevia2/mac_test/mac_test.lpf
									
									
									
									
									
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					BLOCK RESETPATHS ;
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					BLOCK ASYNCPATHS ;
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					LOCATE COMP "clk" SITE "21" ;
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					LOCATE COMP "rst_n" SITE "19" ;
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					LOCATE COMP "rx_p" SITE "94" ;
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					LOCATE COMP "led_n[0]" SITE "37" ;
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					LOCATE COMP "led_n[1]" SITE "38" ;
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					LOCATE COMP "led_n[2]" SITE "39" ;
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					LOCATE COMP "led_n[3]" SITE "40" ;
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					LOCATE COMP "led_n[4]" SITE "43" ;
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					LOCATE COMP "led_n[5]" SITE "44" ;
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					LOCATE COMP "led_n[6]" SITE "45" ;
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					LOCATE COMP "led_n[7]" SITE "46" ;
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					IOBUF PORT "rx_p" IO_TYPE=LVPECL33 ;
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					IOBUF PORT "clk" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[0]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[1]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[2]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[3]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[4]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[5]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[6]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "debug_data[7]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[0]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[1]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[2]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[3]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[4]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[5]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[6]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "led_n[7]" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "tx_n" IO_TYPE=LVCMOS33 ;
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					IOBUF PORT "tx_p" IO_TYPE=LVCMOS33 ;
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					LOCATE COMP "tx_n" SITE "114" ;
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					LOCATE COMP "tx_p" SITE "116" ;
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					LOCATE COMP "button_n[0]" SITE "54" ;
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					LOCATE COMP "debug_data[0]" SITE "73" ;
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					LOCATE COMP "debug_data[1]" SITE "74" ;
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					LOCATE COMP "debug_data[2]" SITE "77" ;
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					LOCATE COMP "debug_data[3]" SITE "87" ;
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					LOCATE COMP "debug_data[4]" SITE "88" ;
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					LOCATE COMP "debug_data[5]" SITE "89" ;
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					LOCATE COMP "debug_data[6]" SITE "90" ;
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					LOCATE COMP "debug_data[7]" SITE "91" ;
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					BLOCK PATH FROM CLKNET "clk_c" TO CLKNET "clk_phy" ;
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					BLOCK PATH FROM CLKNET "clk_phy" TO CLKNET "clk_c" ;
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								demo/lattice_brevia2/mac_test/mac_test1.sty
									
									
									
									
									
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								demo/lattice_brevia2/mac_test/mac_test1.sty
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,206 @@
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					<?xml version="1.0" encoding="UTF-8"?>
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					<!DOCTYPE strategy>
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					<Strategy version="1.0" predefined="0" description="" label="Strategy1">
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					    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
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					    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
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			||||||
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					    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
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					    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
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			||||||
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					    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
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			||||||
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					    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
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					    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
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					    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
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			||||||
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					    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
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			||||||
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					    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
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			||||||
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					    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
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			||||||
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					    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
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			||||||
 | 
					    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_UFMOrder" value="Normal" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_ForceGSRInfer" value="No" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_NumCriticalPaths" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_LST_VHDL2008" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RoutingCDR" value="1" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_parHold" value="On" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynComArea" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_LibPath" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_SYN_VHDL2008" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
 | 
				
			||||||
 | 
					    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
 | 
				
			||||||
 | 
					</Strategy>
 | 
				
			||||||
							
								
								
									
										77
									
								
								design/ledcon.vhd
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										77
									
								
								design/ledcon.vhd
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,77 @@
 | 
				
			|||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
 | 
				
			||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					-- ledcon.vhd : Simple debug LED helper
 | 
				
			||||||
 | 
					--   To blink or not blink.
 | 
				
			||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					-- Author       : Markus Koch <markus@notsyncing.net>
 | 
				
			||||||
 | 
					-- Contributors : None
 | 
				
			||||||
 | 
					-- License      : Mozilla Public License (MPL) Version 2
 | 
				
			||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					library ieee;
 | 
				
			||||||
 | 
					use ieee.std_logic_1164.all;
 | 
				
			||||||
 | 
					use ieee.numeric_std.all;
 | 
				
			||||||
 | 
					use ieee.math_real.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					entity ledcon is
 | 
				
			||||||
 | 
						generic(
 | 
				
			||||||
 | 
							F_CLK : integer;
 | 
				
			||||||
 | 
							BLINK : boolean_vector
 | 
				
			||||||
 | 
						);
 | 
				
			||||||
 | 
						port(
 | 
				
			||||||
 | 
							clk   : in  std_logic;
 | 
				
			||||||
 | 
							rst   : in  std_logic;
 | 
				
			||||||
 | 
							sig   : in  std_logic_vector;
 | 
				
			||||||
 | 
							led_n : out std_logic_vector
 | 
				
			||||||
 | 
						);
 | 
				
			||||||
 | 
					end entity ledcon;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					architecture RTL of ledcon is
 | 
				
			||||||
 | 
						constant MS_CNT_MAX : integer := integer(round(real(F_CLK) * (1.0 * 10.0 ** (-3))));
 | 
				
			||||||
 | 
						signal ms_cnt       : integer range 0 to MS_CNT_MAX;
 | 
				
			||||||
 | 
						signal ms_tick      : std_logic;
 | 
				
			||||||
 | 
					begin
 | 
				
			||||||
 | 
						mstimer : process(clk, rst) is
 | 
				
			||||||
 | 
						begin
 | 
				
			||||||
 | 
							if rst then
 | 
				
			||||||
 | 
								ms_cnt <= MS_CNT_MAX;
 | 
				
			||||||
 | 
							elsif rising_edge(clk) then
 | 
				
			||||||
 | 
								if (ms_cnt = 0) then
 | 
				
			||||||
 | 
									ms_cnt <= MS_CNT_MAX;
 | 
				
			||||||
 | 
								else
 | 
				
			||||||
 | 
									ms_cnt <= ms_cnt - 1;
 | 
				
			||||||
 | 
								end if;
 | 
				
			||||||
 | 
							end if;
 | 
				
			||||||
 | 
						end process mstimer;
 | 
				
			||||||
 | 
						ms_tick <= '1' when ms_cnt = 0 else '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						ledcongen : for i in sig'low to sig'high generate
 | 
				
			||||||
 | 
							ledblock : block
 | 
				
			||||||
 | 
								constant LED_CNT_MAX : integer := 50; -- on time, in ms
 | 
				
			||||||
 | 
								constant LED_CNT_MIN : integer := -50; -- off time, in ms
 | 
				
			||||||
 | 
								signal led_cnt       : integer range LED_CNT_MIN to LED_CNT_MAX;
 | 
				
			||||||
 | 
							begin
 | 
				
			||||||
 | 
								ledgen : if BLINK(i) generate
 | 
				
			||||||
 | 
									ledproc : process(clk, rst) is
 | 
				
			||||||
 | 
									begin
 | 
				
			||||||
 | 
										if rst then
 | 
				
			||||||
 | 
											led_cnt <= LED_CNT_MIN;
 | 
				
			||||||
 | 
										elsif rising_edge(clk) then
 | 
				
			||||||
 | 
											if (led_cnt = LED_CNT_MIN) then
 | 
				
			||||||
 | 
												if sig(i) then
 | 
				
			||||||
 | 
													led_cnt <= LED_CNT_MAX;
 | 
				
			||||||
 | 
												end if;
 | 
				
			||||||
 | 
											elsif ms_tick then
 | 
				
			||||||
 | 
												led_cnt <= led_cnt - 1;
 | 
				
			||||||
 | 
											end if;
 | 
				
			||||||
 | 
										end if;
 | 
				
			||||||
 | 
									end process ledproc;
 | 
				
			||||||
 | 
									led_n(i) <= '0' when led_cnt > 0 else '1';
 | 
				
			||||||
 | 
								else generate
 | 
				
			||||||
 | 
									led_n(i) <= not sig(i);
 | 
				
			||||||
 | 
								end generate ledgen;
 | 
				
			||||||
 | 
							end block ledblock;
 | 
				
			||||||
 | 
						end generate ledcongen;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					end architecture RTL;
 | 
				
			||||||
							
								
								
									
										212
									
								
								design/top_mac_test.vhd
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										212
									
								
								design/top_mac_test.vhd
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,212 @@
 | 
				
			|||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
 | 
				
			||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					-- top_mac_test.vhd: Test design to verify the functionality of the MAC core
 | 
				
			||||||
 | 
					--   Sends a broadcast with 100 decrementing numbers every 250 ms or when a
 | 
				
			||||||
 | 
					--   button is pushed. It will also directly reply with that content to any
 | 
				
			||||||
 | 
					--   packet addressed to us.
 | 
				
			||||||
 | 
					--
 | 
				
			||||||
 | 
					--   Target: Lattice Brevia 2 (LFXP2-5E)
 | 
				
			||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					-- Author       : Markus Koch <markus@notsyncing.net>
 | 
				
			||||||
 | 
					-- Contributors : None
 | 
				
			||||||
 | 
					-- License      : Mozilla Public License (MPL) Version 2
 | 
				
			||||||
 | 
					-- -------------------------------------------------------------------------- --
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					library ieee;
 | 
				
			||||||
 | 
					use ieee.std_logic_1164.all;
 | 
				
			||||||
 | 
					use ieee.numeric_std.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					use ieee.math_real.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					library trashernet;
 | 
				
			||||||
 | 
					use trashernet.trashernet_pkg.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					entity top_mac_test is
 | 
				
			||||||
 | 
						port(
 | 
				
			||||||
 | 
							clk        : in  std_logic;
 | 
				
			||||||
 | 
							rst_n      : in  std_logic;
 | 
				
			||||||
 | 
							rx_p       : in  std_logic;
 | 
				
			||||||
 | 
							tx_p       : out std_logic;
 | 
				
			||||||
 | 
							tx_n       : out std_logic;
 | 
				
			||||||
 | 
							led_n      : out std_logic_vector(7 downto 0);
 | 
				
			||||||
 | 
							button_n   : in  std_logic_vector(3 downto 0);
 | 
				
			||||||
 | 
							debug_data : out std_logic_vector(7 downto 0)
 | 
				
			||||||
 | 
						);
 | 
				
			||||||
 | 
					end entity top_mac_test;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					architecture rtl of top_mac_test is
 | 
				
			||||||
 | 
						component pll0
 | 
				
			||||||
 | 
							port(
 | 
				
			||||||
 | 
								CLK   : in  std_logic;
 | 
				
			||||||
 | 
								CLKOP : out std_logic;
 | 
				
			||||||
 | 
								LOCK  : out std_logic
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
						end component pll0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						constant F_CLK     : integer := 50000000;
 | 
				
			||||||
 | 
						constant F_CLK_PHY : integer := 140000000;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						constant LED_BLINK : boolean_vector(led_n'range) := (
 | 
				
			||||||
 | 
							6 downto 2 => true,
 | 
				
			||||||
 | 
							others     => false
 | 
				
			||||||
 | 
						);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						constant ETH_CONFIG : configuration_t := (
 | 
				
			||||||
 | 
							mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
 | 
				
			||||||
 | 
						);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						signal rst          : std_logic;
 | 
				
			||||||
 | 
						signal clk_phy      : std_logic;
 | 
				
			||||||
 | 
						signal phy_pll_lock : std_logic;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						signal led_sig : std_logic_vector(led_n'range);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						signal phy_out : phy_out_t;
 | 
				
			||||||
 | 
						signal phy_in  : phy_in_t;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						signal mac_out : mac_out_t;
 | 
				
			||||||
 | 
						signal mac_in  : mac_in_t;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						type status_t is (IDLE, TX, WAITDONE);
 | 
				
			||||||
 | 
						signal state          : status_t;
 | 
				
			||||||
 | 
						constant BYTE_CNT_MAX : integer := 100;
 | 
				
			||||||
 | 
						signal byte_cnt       : integer range 0 to BYTE_CNT_MAX;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						signal button_n_sync : std_logic_vector(button_n'range);
 | 
				
			||||||
 | 
						signal button        : std_logic_vector(button_n'range);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1;
 | 
				
			||||||
 | 
						signal tmo       : integer range 0 to TMO_MAX;
 | 
				
			||||||
 | 
					begin
 | 
				
			||||||
 | 
						trashernet_mac_inst : entity trashernet.trashernet_mac
 | 
				
			||||||
 | 
							port map(
 | 
				
			||||||
 | 
								clk     => clk,
 | 
				
			||||||
 | 
								rst     => rst,
 | 
				
			||||||
 | 
								phy_out => phy_out,
 | 
				
			||||||
 | 
								phy_in  => phy_in,
 | 
				
			||||||
 | 
								mac_out => mac_out,
 | 
				
			||||||
 | 
								mac_in  => mac_in
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						pll0_inst : pll0
 | 
				
			||||||
 | 
							port map(
 | 
				
			||||||
 | 
								CLK   => clk,
 | 
				
			||||||
 | 
								CLKOP => clk_phy,
 | 
				
			||||||
 | 
								LOCK  => phy_pll_lock
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
 | 
				
			||||||
 | 
							generic map(
 | 
				
			||||||
 | 
								F_CLK     => F_CLK,
 | 
				
			||||||
 | 
								F_CLK_PHY => F_CLK_PHY
 | 
				
			||||||
 | 
							)
 | 
				
			||||||
 | 
							port map(
 | 
				
			||||||
 | 
								clk     => clk,
 | 
				
			||||||
 | 
								phy_clk => clk_phy,
 | 
				
			||||||
 | 
								rst     => rst,
 | 
				
			||||||
 | 
								phy_out => phy_out,
 | 
				
			||||||
 | 
								phy_in  => phy_in,
 | 
				
			||||||
 | 
								rx_p    => rx_p,
 | 
				
			||||||
 | 
								tx_p    => tx_p,
 | 
				
			||||||
 | 
								tx_n    => tx_n
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						reset_sync : process(clk, rst_n) is
 | 
				
			||||||
 | 
						begin
 | 
				
			||||||
 | 
							if (rst_n = '0') then
 | 
				
			||||||
 | 
								rst <= '1';
 | 
				
			||||||
 | 
							elsif (rising_edge(clk)) then
 | 
				
			||||||
 | 
								rst <= '0';
 | 
				
			||||||
 | 
							end if;
 | 
				
			||||||
 | 
						end process reset_sync;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						ledcon_inst : entity work.ledcon
 | 
				
			||||||
 | 
							generic map(
 | 
				
			||||||
 | 
								F_CLK => F_CLK,
 | 
				
			||||||
 | 
								BLINK => LED_BLINK
 | 
				
			||||||
 | 
							)
 | 
				
			||||||
 | 
							port map(
 | 
				
			||||||
 | 
								clk   => clk,
 | 
				
			||||||
 | 
								rst   => rst,
 | 
				
			||||||
 | 
								sig   => led_sig,
 | 
				
			||||||
 | 
								led_n => led_n
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						led_sig <= (
 | 
				
			||||||
 | 
							0 => phy_pll_lock,
 | 
				
			||||||
 | 
							1 => phy_out.carrier_detect,
 | 
				
			||||||
 | 
							2 => phy_out.rx_active,
 | 
				
			||||||
 | 
							3 => phy_out.rx_error,
 | 
				
			||||||
 | 
							4 => mac_out.rx_mac_crc_ok,
 | 
				
			||||||
 | 
							5 => mac_out.rx_mac_crc_error,
 | 
				
			||||||
 | 
							6 => mac_out.tx_active,
 | 
				
			||||||
 | 
							7 => '0'
 | 
				
			||||||
 | 
						);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						synchronizer_inst : entity trashernet.synchronizer
 | 
				
			||||||
 | 
							generic map(
 | 
				
			||||||
 | 
								SIZE => 2
 | 
				
			||||||
 | 
							)
 | 
				
			||||||
 | 
							port map(
 | 
				
			||||||
 | 
								clk      => clk,
 | 
				
			||||||
 | 
								rst      => rst,
 | 
				
			||||||
 | 
								data_in  => button_n(0),
 | 
				
			||||||
 | 
								data_out => button_n_sync(0)
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						button <= not button_n_sync;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						receiver : process(clk, rst) is
 | 
				
			||||||
 | 
						begin
 | 
				
			||||||
 | 
							if rst then
 | 
				
			||||||
 | 
								state                 <= IDLE;
 | 
				
			||||||
 | 
								mac_in.tx_mac_data_en <= '0';
 | 
				
			||||||
 | 
								tmo                   <= 0;
 | 
				
			||||||
 | 
							elsif rising_edge(clk) then
 | 
				
			||||||
 | 
								if (tmo /= 0) then
 | 
				
			||||||
 | 
									tmo <= tmo - 1;
 | 
				
			||||||
 | 
								end if;
 | 
				
			||||||
 | 
								case state is
 | 
				
			||||||
 | 
									when IDLE =>
 | 
				
			||||||
 | 
										if mac_out.rx_mac_crc_ok then
 | 
				
			||||||
 | 
											if (mac_out.rx_header.mac_destination = ETH_CONFIG.mac_address) then -- Note: We won't respond to broadcasts!
 | 
				
			||||||
 | 
												state                            <= TX;
 | 
				
			||||||
 | 
												byte_cnt                         <= BYTE_CNT_MAX;
 | 
				
			||||||
 | 
												mac_in.tx_header.mac_destination <= mac_out.rx_header.mac_source;
 | 
				
			||||||
 | 
											end if;
 | 
				
			||||||
 | 
										end if;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
										if (tmo = 0) or (button(0) = '1') then
 | 
				
			||||||
 | 
											state                            <= TX;
 | 
				
			||||||
 | 
											byte_cnt                         <= BYTE_CNT_MAX;
 | 
				
			||||||
 | 
											mac_in.tx_header.mac_destination <= (others => x"FF");
 | 
				
			||||||
 | 
										end if;
 | 
				
			||||||
 | 
									when TX =>
 | 
				
			||||||
 | 
										tmo                            <= TMO_MAX;
 | 
				
			||||||
 | 
										mac_in.tx_header.mac_ethertype <= (x"00", std_logic_vector(to_unsigned(BYTE_CNT_MAX, 8)));
 | 
				
			||||||
 | 
										mac_in.tx_mac_data_en          <= '1';
 | 
				
			||||||
 | 
										mac_in.tx_mac_data             <= std_logic_vector(to_unsigned(byte_cnt, 8));
 | 
				
			||||||
 | 
										if mac_out.tx_mac_data_ack then
 | 
				
			||||||
 | 
											if byte_cnt = 1 then
 | 
				
			||||||
 | 
												mac_in.tx_mac_data_en <= '0';
 | 
				
			||||||
 | 
												state                 <= WAITDONE;
 | 
				
			||||||
 | 
											else
 | 
				
			||||||
 | 
												byte_cnt <= byte_cnt - 1;
 | 
				
			||||||
 | 
											end if;
 | 
				
			||||||
 | 
										end if;
 | 
				
			||||||
 | 
									when WAITDONE =>
 | 
				
			||||||
 | 
										if mac_out.tx_active = '0' then
 | 
				
			||||||
 | 
											state <= IDLE;
 | 
				
			||||||
 | 
										end if;
 | 
				
			||||||
 | 
								end case;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							end if;
 | 
				
			||||||
 | 
						end process receiver;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						mac_in.tx_header.mac_source <= ETH_CONFIG.mac_address;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						debug_data(0) <= tx_p;
 | 
				
			||||||
 | 
						debug_data(1) <= tx_n;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					end architecture rtl;
 | 
				
			||||||
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		Reference in New Issue
	
	Block a user