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phy: Rename rx/tx signals

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This commit is contained in:
Markus Koch 2021-08-28 19:08:37 +02:00
parent 3900d454f9
commit d16f1afd9a
1 changed files with 13 additions and 13 deletions
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26
trashernet/trashernet_phy.vhd
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@ -5,7 +5,7 @@ use ieee.math_real.all;
entity trashernet_phy is
generic(
F_CLK : in integer
F_CLK : in integer -- Clock frequency
);
port(
-- Global
@ -13,16 +13,16 @@ entity trashernet_phy is
rst : in std_logic; -- Asynchronous reset
-- Eth
data_rx : out std_logic_vector(7 downto 0); -- RX Data
data_rx_valid : out std_logic; -- RX Data valid
rx_data : out std_logic_vector(7 downto 0); -- RX Data
rx_data_valid : out std_logic; -- RX Data valid
rx_active : out std_logic; -- RX of packet in progress
data_tx : in std_logic_vector(7 downto 0); -- TX Data
data_tx_en : in std_logic;
data_tx_ack : out std_logic; --
tx_data : in std_logic_vector(7 downto 0); -- TX Data
tx_data_en : in std_logic; -- Transmitter enable
tx_data_ack : out std_logic; -- Latched data_tx
carrier_detect : out std_logic; --
rx_error : out std_logic; --
carrier_detect : out std_logic; -- Carrier detected
rx_error : out std_logic; -- Receive error
-- Ethernet physical signals
rx_p : in std_logic;
@ -212,17 +212,17 @@ begin
bytizer : process(clk, rst) is
begin
if rst then
data_rx_valid <= '0';
data_rx <= (others => '0');
rx_data_valid <= '0';
rx_data <= (others => '0');
elsif rising_edge(clk) then
data_rx_valid <= '0';
rx_data_valid <= '0';
if rx_active then
if (bit_stb) then
data_rx <= bit_value & data_rx(data_rx'high downto data_rx'low + 1);
rx_data <= bit_value & rx_data(rx_data'high downto rx_data'low + 1);
if (bit_cnt = 7) then
data_rx_valid <= '1';
rx_data_valid <= '1';
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1;