fpga/trashernet
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base: fpga:afb545cd021961aee6f4d66259116d194454465e
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fpga:master
fpga:feature/trashernet-soc
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1
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compare: fpga:d1e0143c9dd6bb9c893d8fa4a185f3900d45463e
Branches Tags
fpga:feature/trashernet-soc
fpga:master
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1

2 Commits
afb545cd02 ... d1e0143c9d

Author SHA1 Message Date
Markus Koch
d1e0143c9d phy: Fix TX manchester encoding 
Ethernet uses "inverted" manchester as per IEEE 802.3.
 2022-01-23 16:02:31 +01:00
Markus Koch
1bcddf4273 phy: Improve NLP timeout accuracy 2022-01-23 16:01:33 +01:00
1 changed files with 3 additions and 3 deletions
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6
trashernet/trashernet_phy.vhd
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@ -56,7 +56,7 @@ begin
signal bit_cnt : integer range 0 to 7;
-- NLP supervision
constant NLP_TIMEOUT_CNT_MAX : integer := integer(round(real(F_CLK) * 16.0 * 10.0 ** (-3))); -- Every 16 ms
constant NLP_TIMEOUT_CNT_MAX : integer := integer(round(real(F_CLK) * 16.0 * 10.0 ** (-3))) - 1; -- Every 16 ms
signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX;
begin
-- Synchronize RX input
@ -396,8 +396,8 @@ begin
tx_p <= '1';
tx_n <= '0';
when ACTIVE =>
tx_p <= sr(sr'low) xor bit_stage;
tx_n <= not (sr(sr'low) xor bit_stage);
tx_p <= sr(sr'low) xnor bit_stage;
tx_n <= not (sr(sr'low) xnor bit_stage);
end case;
end if;
end process driver;