design/top_hwitl.vhd

@@ -26,9 +26,9 @@ entity top_hwitl is
 		rx_p       : in  std_logic;
 		tx_p       : out std_logic;
 		tx_n       : out std_logic;
-		led_n      : out std_logic_vector(7 downto 0); -- @suppress: Used in different architectures
+		led_n      : out std_logic_vector(7 downto 0);
-		button_n   : in  std_logic_vector(3 downto 0); -- @suppress: Used in different architectures
+		button_n   : in  std_logic_vector(3 downto 0);
-		debug_data : out std_logic_vector(7 downto 0) -- @suppress: Used in different architectures
+		debug_data : out std_logic_vector(7 downto 0)
 	);
 end entity top_hwitl;
 
@@ -50,6 +50,7 @@ architecture mac of top_hwitl is
 
 	signal rst          : std_logic;
 	signal clk_phy      : std_logic;
+	signal phy_pll_lock : std_logic;
 
 	signal phy_out : phy_out_t;
 	signal phy_in  : phy_in_t;
@@ -79,7 +80,7 @@ begin
 		port map(
 			CLK   => clk,
 			CLKOP => clk_phy,
-			LOCK  => open
+			LOCK  => phy_pll_lock
 		);
 
 	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
@@ -191,6 +192,7 @@ architecture eth of top_hwitl is
 
 	signal rst          : std_logic;
 	signal clk_phy      : std_logic;
+	signal phy_pll_lock : std_logic;
 
 	signal phy_out : phy_out_t;
 	signal phy_in  : phy_in_t;
@@ -214,12 +216,12 @@ architecture eth of top_hwitl is
 begin
 	trashernet_arp_inst : entity trashernet.trashernet_arp
 		generic map(
-			SYSTICK_FREQ => F_CLK
+			TIMEOUT_TICK_FREQ => F_CLK
 		)
 		port map(
 			clk             => clk,
 			rst             => rst,
-			systick         => '1',
+			timeout_tick    => '1',
 			mac_config      => ETH_CONFIG,
 			ip_config       => IP_CONFIG,
 			arp_out         => arp_out,
@@ -228,13 +230,6 @@ begin
 			ethernet_ii_in  => ethernet_ii_in(PROT_ARP)
 		);
 
-	ethernet_i_in <= ethernet_i_in_t'(
-		tx_mac_address => (others => (others => '-')),
-		tx_data        => (others => '-'),
-		tx_en          => '0',
-		tx_length      => (others => '-')
-	);
-
 	trashernet_eth_inst : entity trashernet.trashernet_eth
 		generic map(
 			ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
@@ -265,7 +260,7 @@ begin
 		port map(
 			CLK   => clk,
 			CLKOP => clk_phy,
-			LOCK  => open
+			LOCK  => phy_pll_lock
 		);
 
 	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc

trashernet/trashernet_arp.vhd

@@ -17,13 +17,13 @@ use work.trashernet_pkg.all;
 
 entity trashernet_arp is
 	generic(
-		SYSTICK_FREQ : integer
+		TIMEOUT_TICK_FREQ : integer
 	);
 	port(
 		-- Global
 		clk             : in  std_logic; -- Global clock
 		rst             : in  std_logic; -- Asynchronous reset
-		systick         : in  std_logic; -- Global time reference for slow events (here: timeout)
+		timeout_tick    : in  std_logic; -- Global timeout tick strobe
 
 		-- Configuration
 		mac_config      : in  configuration_t; -- Trashernet MAC configuration
@@ -124,14 +124,14 @@ begin
 
 		timeout_timer_inst : entity work.timer
 			generic map(
-				F_TICK    => SYSTICK_FREQ,
+				F_TICK    => TIMEOUT_TICK_FREQ,
 				DURATION  => ARP_TIMEOUT,
 				AUTOSTART => false
 			)
 			port map(
 				clk         => clk,
 				rst         => rst,
-				tick        => systick,
+				tick        => timeout_tick,
 				start       => arp_tx_request_rq,
 				expired     => query_timeout,
 				expired_stb => open
@@ -155,7 +155,7 @@ begin
 		constant SR_ADDRESSES_OFFSET : integer := -8;
 		alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET);
 		alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET);
-		alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC
+		alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET);
 		alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET);
 
 		type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE);
@@ -240,7 +240,7 @@ begin
 							state     <= HEAD;
 						end if;
 
-					when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err)
+					when IGNORE =>
 						null;
 				end case;
 			end if;

trashernet/trashernet_mac.vhd

@@ -102,7 +102,7 @@ begin
 								byte_count <= byte_count + 1;
 							end if;
 						end if;
-					when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error)
+					when PAYLOAD =>
 						if phy_out.rx_data_valid then
 							sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
 							if byte_count = CRC_LENGTH then

trashernet/trashernet_phy_cdc.vhd

@@ -47,8 +47,6 @@ architecture rtl of trashernet_phy_cdc is
 	signal rx_data_valid_i : std_logic;
 
 begin
-	assert F_CLK_PHY > 2 * F_CLK report "F_CLK_PHY must be at least 2x F_CLK" severity failure;
-	
 	-- -------------------------------------------------------------------------
 	-- Drives: PHY clock domain
 	-- -------------------------------------------------------------------------

trashernet/trashernet_pkg.vhd

@@ -82,7 +82,7 @@ package trashernet_pkg is
 		ethertype : ethertype_t;
 	end record;
 	type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
-	constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic
+	constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- NULL range
 	constant ETHERNET_II_PROTOCOL_IP    : ethernet_ii_protocol_t               := (ethertype => (x"08", x"00"));
 	constant ETHERNET_II_PROTOCOL_ARP   : ethernet_ii_protocol_t               := (ethertype => (x"08", x"06"));