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wip/cococi
Author | SHA1 | Date | |
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9f2f3223e5 | |||
64f6197dbb |
@ -18,10 +18,10 @@ use work.bench_pkg.all;
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library trashernet;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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use trashernet.trashernet_pkg.all;
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entity bench_trashernet_phy is
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entity cocotb_trashernet_phy is
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end entity bench_trashernet_phy;
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end entity cocotb_trashernet_phy;
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architecture bench of bench_trashernet_phy is
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architecture bench of cocotb_trashernet_phy is
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signal clk : std_logic;
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal rst : std_logic;
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4
cocotb/.gitignore
vendored
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4
cocotb/.gitignore
vendored
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@ -0,0 +1,4 @@
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*.pyc
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*.o
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results.xml
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*.cf
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14
cocotb/Makefile
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14
cocotb/Makefile
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@ -0,0 +1,14 @@
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# defaults
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SIM ?= ghdl
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TOPLEVEL_LANG ?= vhdl
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BASE = $(PWD)/..
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COMPILE_ARGS=--std=08
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VHDL_SOURCES_trashernet += $(BASE)/trashernet/*.vhd
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VHDL_SOURCES += $(BASE)/cocotb/*.vhd
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TOPLEVEL = cocotb_trashernet_phy
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MODULE = cocotb_trashernet_phy
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include $(shell cocotb-config --makefiles)/Makefile.sim
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90
cocotb/cocotb_trashernet_phy.py
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90
cocotb/cocotb_trashernet_phy.py
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@ -0,0 +1,90 @@
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#!/usr/bin/env python
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import cocotb
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from cocotb.triggers import *
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from cocotb.result import *
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from cocotb.queue import Queue
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# DUT interface (internal)
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tb_rx_queue = Queue()
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tb_rx_queue_done_ev = Event()
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async def dut_receiver(dut):
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scoreboard = tb_rx_queue
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while True:
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await Edge(dut.coco_dut_rxs)
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byte = dut.coco_dut_rxd.value
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dut._log.info("[DT:RX <-] Byte %02X", byte)
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assert not scoreboard.empty(), "Data was provided on the RX interface even though none was expected"
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if not scoreboard.empty():
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sb_byte = await scoreboard.get()
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assert byte == sb_byte, f"Received {byte} instead of {sb_byte}"
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async def dut_rxa(dut):
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scoreboard = tb_rx_queue
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await Edge(dut.coco_dut_rxa) # TODO: Workaround for some stupid bug somewhere
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while True:
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await Edge(dut.coco_dut_rxa)
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if dut.coco_dut_rxa.value:
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dut._log.info("[DT:RX <-] Start of frame")
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else:
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dut._log.info("[DT:RX <-] End of frame")
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if scoreboard.empty():
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tb_rx_queue_done_ev.set()
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# TB / ETH interface (external)
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tb_tx_queue = Queue()
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async def tb_transmitter(dut):
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queue = tb_tx_queue
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while True:
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byte = await queue.get()
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if byte == -1:
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dut._log.info("[TB:TX ->] Wait IPG")
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await Timer(16, units="us") # IPG
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else: # TX byte
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dut._log.info("[TB:TX ->] Byte %02X", byte)
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dut.coco_tb_txd.value = byte
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dut.coco_tb_txs.value = not dut.coco_tb_txs.value
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await Edge(dut.coco_tb_txa);
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async def tb_send_packet(dut, data):
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queue = tb_tx_queue
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scoreboard = tb_rx_queue
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queue.put_nowait(0x55)
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queue.put_nowait(0x55)
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queue.put_nowait(0x55)
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queue.put_nowait(0xD5)
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for byte in data:
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scoreboard.put_nowait(byte)
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queue.put_nowait(byte)
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queue.put_nowait(-1)
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async def timeout(dut):
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await Timer(50, units="us")
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assert False, "Timeout"
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@cocotb.test()
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async def simple_rx(dut):
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"""Receive a packet using trashernet."""
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await cocotb.start(timeout(dut))
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await cocotb.start(dut_receiver(dut))
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await cocotb.start(dut_rxa(dut))
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await cocotb.start(tb_transmitter(dut))
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dut.rst.value = 1
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await Timer(20, units="ns")
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dut.rst.value = 0
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await Timer(20, units="ns")
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await tb_send_packet(dut, b'\x02\x03\x05\x07')
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await cocotb.start(timeout(dut))
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await tb_rx_queue_done_ev.wait()
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104
cocotb/cocotb_trashernet_phy.vhd
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104
cocotb/cocotb_trashernet_phy.vhd
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@ -0,0 +1,104 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- bench_trashernet_phy.vhd : Cocotb test bench for the PHY
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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entity cocotb_trashernet_phy is
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end entity cocotb_trashernet_phy;
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architecture bench of cocotb_trashernet_phy is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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-- Cocotb interface
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signal coco_dut_rxd : std_logic_vector(7 downto 0); -- RX data
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signal coco_dut_rxs : std_logic := '0'; -- RX toggle
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signal coco_dut_rxa : std_logic; -- RX active
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signal coco_tb_txd : std_logic_vector(7 downto 0); -- TX data
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signal coco_tb_txs : std_logic := '0'; -- TX toggle
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signal coco_tb_txa : std_logic := '0'; -- TX done toggle
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begin
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-- Instantiate design
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => 49000000,
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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-- Create infrastructure
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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phy_clock_driver : process
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constant period : time := 10 ns;
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begin
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phy_clk <= '0';
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wait for period / 2;
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phy_clk <= '1';
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wait for period / 2;
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end process phy_clock_driver;
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-- Cocotb adapter (ETH)
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test : process is
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begin
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rx_p <= '0';
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loop
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wait on coco_tb_txs;
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for j in coco_tb_txd'low to coco_tb_txd'high loop
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rx_p <= not coco_tb_txd(j);
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wait for 50 ns;
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rx_p <= coco_tb_txd(j);
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wait for 50 ns;
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end loop;
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coco_tb_txa <= not coco_tb_txa;
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end loop;
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end process test;
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receiver : process is
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begin
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wait until rising_edge(clk);
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if phy_out.rx_data_valid then
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coco_dut_rxd <= phy_out.rx_data;
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coco_dut_rxs <= not coco_dut_rxs;
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end if;
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end process receiver;
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coco_dut_rxa <= phy_out.rx_active;
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end architecture bench;
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