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PHY:TX: Improve handling of NLP timing generation #6

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opened 2022-01-23 16:55:43 +01:00 by markus · 1 comment
markus commented 2022-01-23 16:55:43 +01:00
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Currently, BIT_CNT_MAX_NLP causes the bit_cnt register to be 18 bits wide. This kills our timing. Don't do that.

Currently, `BIT_CNT_MAX_NLP` causes the bit_cnt register to be 18 bits wide. This kills our timing. Don't do that.
markus added the
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markus added this to the PHY + MAC milestone 2022-01-23 16:55:55 +01:00
markus commented 2022-01-29 20:26:53 +01:00
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Fixed in 075f935e12.

Fixed in 075f935e12dd7d20fe7b20331bc3bef2e10e435f.
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Reference: fpga/trashernet#6
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