167 lines
5.3 KiB
VHDL
167 lines
5.3 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- bench_trashernet_mac.vhd : Stimulus-only test bench for the MAC+PHY parts
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-- Tests TX path through the RX path. Not great, but whatever.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.bench_pkg.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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entity bench_trashernet_mac is
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end entity bench_trashernet_mac;
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architecture bench of bench_trashernet_mac is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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constant TEST_BENCH_LOOPBACK : boolean := true;
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begin
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => 49000000,
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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mac_out => mac_out,
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mac_in => mac_in
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);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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phy_clock_driver : process
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constant period : time := 10 ns;
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begin
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phy_clk <= '0';
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wait for period / 2;
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phy_clk <= '1';
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wait for period / 2;
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end process phy_clock_driver;
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rstsim : process is
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begin
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rst <= '1';
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wait for 20 ns;
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rst <= '0';
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wait for 20 ns;
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wait;
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end process rstsim;
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loopbackmode : if TEST_BENCH_LOOPBACK generate
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rx_p <= tx_p;
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else generate
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test : process is
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begin
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wait until rst = '0';
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wait for 10 ns;
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rx_p <= '0';
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send_data(rx_p, byte_vector'(
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x"55", x"55", x"55", x"D5",
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x"11", x"22", x"33", x"44", x"55", x"66", x"00", x"e0", x"4c", x"36", x"00", x"2f", x"08", x"00", x"45", x"00", x"00", x"54", x"fe", x"22", x"40", x"00", x"40", x"01", x"f5", x"28", x"c0", x"a8", x"63", x"0a", x"c0", x"a8", x"63", x"02", x"08", x"00", x"90", x"e6", x"00", x"06", x"00", x"01", x"da", x"bd", x"2c", x"61", x"00", x"00", x"00", x"00", x"9f", x"20", x"02", x"00", x"00", x"00", x"00", x"00", x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b", x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28", x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37",
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x"e9", x"f2", x"6b", x"30"
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));
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send_data(rx_p, byte_vector'(
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x"55", x"55", x"55", x"D5",
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x"11", x"22", x"33", x"44", x"55", x"66", x"00", x"e0", x"4c", x"36", x"00", x"2f", x"08", x"00", x"45", x"00", x"00", x"54", x"ca", x"78", x"40", x"00", x"40", x"01", x"28", x"d4", x"c0", x"a8", x"63", x"0a", x"c0", x"a8", x"63", x"01", x"08", x"00", x"93", x"f5", x"00", x"03", x"00", x"01", x"3c", x"bc", x"2c", x"61", x"00", x"00", x"00", x"00", x"38", x"16", x"04", x"00", x"00", x"00", x"00", x"00", x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b", x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28", x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37",
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x"b9", x"7f", x"c7", x"91"
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));
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send_data(rx_p, byte_vector'(
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x"55", x"55", x"55", x"D5",
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x"12", x"34", x"56", x"78", x"90", x"12",
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x"AB", x"CD", x"EF", x"AA", x"BB", x"CC",
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x"08", x"00",
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x"11", x"22", x"33", x"44", x"55", x"66",
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x"CC", x"2C", x"CC", x"2C"
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));
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wait;
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end process test;
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end generate loopbackmode;
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receiver : process is
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begin
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wait until rising_edge(clk);
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if phy_out.rx_data_valid then
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report "[PHY] RX byte: " & to_hstring(phy_out.rx_data);
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end if;
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if mac_out.rx_mac_valid then
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report "[MAC] RX byte: " & to_hstring(mac_out.rx_mac_data);
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end if;
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if mac_out.rx_mac_crc_ok then
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report "[MAC] RX CRC OK";
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end if;
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if mac_out.rx_mac_crc_error then
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report "[MAC] RX CRC error";
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end if;
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end process receiver;
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mac_tx : process is
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begin
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mac_in.tx_mac_data <= x"11";
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mac_in.tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
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mac_in.tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
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mac_in.tx_header.mac_ethertype <= (x"01", x"00");
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mac_in.tx_mac_data_en <= '0';
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wait until rst = '0';
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wait for 100 ns;
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mac_in.tx_mac_data_en <= '1';
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wait until rising_edge(mac_out.tx_mac_data_ack);
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wait until rising_edge(mac_out.tx_mac_data_ack);
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wait until rising_edge(mac_out.tx_mac_data_ack);
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wait until rising_edge(clk);
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mac_in.tx_mac_data_en <= '0';
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wait;
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end process mac_tx;
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end architecture bench;
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