38 lines
1.9 KiB
Markdown
38 lines
1.9 KiB
Markdown
# Trashernet
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Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:
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* Layer 1, Physical: `trashernet_phy`
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* Layer 2, Data link: `trashernet_mac`
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When writing it, the following were the main design philosophies:
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1. Standards are nice and all, but this, it just needs to work.
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2. Hardware is expensive, LOC are not. So let's do everything we can inside the FPGA.
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3. If there's a feature that feels optional even though it isn't, it is. See 1. if in doubt.
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**IMPORTANT:** This code (and HW suggestions) violate the Ethernet standard in many ways. Do not use in proper (especially commercial) products.
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## Hardware
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* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
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* TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)
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Notes:
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* The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
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* On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
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## License
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This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.
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The Trashernet logo uses graphics from [svgrepo.com](https://svgrepo.com), which are released under the Creative Commons CC0 license, granting the right to freely adapt and use them in any context. Thank you for making these available:
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* Trash can: https://www.svgrepo.com/svg/66604/trash
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* Ethernet jack: https://www.svgrepo.com/svg/292518/ethernet
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