Markus Koch markus
markus pushed to feature/mac at fpga/trashernet 2022-01-30 19:25:26 +01:00
61812c133f phy: Improve header synchronization
markus closed issue fpga/trashernet#2 2022-01-30 18:06:55 +01:00
PHY: Don't process Manchester timing right from the start
markus commented on issue fpga/trashernet#2 2022-01-30 18:02:48 +01:00
PHY: Don't process Manchester timing right from the start

Fix in a different way in a5142f9abbb99992abe4201f3ad587159ffcb7ec.

markus pushed to feature/mac at fpga/trashernet 2022-01-30 18:01:56 +01:00
a5142f9abb des: Improve header synchronization
markus pushed to dev at markus/lifomapserver 2022-01-30 10:50:02 +01:00
6519c019c9 htdocs: Make oceans less eye-searing
markus commented on issue fpga/trashernet#6 2022-01-29 20:26:53 +01:00
PHY:TX: Improve handling of NLP timing generation

Fixed in 075f935e12dd7d20fe7b20331bc3bef2e10e435f.

markus closed issue fpga/trashernet#6 2022-01-29 20:26:53 +01:00
PHY:TX: Improve handling of NLP timing generation
markus pushed to master at fpga/trashernet 2022-01-29 20:26:21 +01:00
075f935e12 phy: Fix NLPs
markus pushed to feature/mac at fpga/trashernet 2022-01-29 20:25:05 +01:00
075f935e12 phy: Fix NLPs
markus commented on issue electronics/mini-poe-relay#2 2022-01-25 22:25:46 +01:00
RX Data

Hmmm maybe instead of the pull-up, we can do implement a better link-detection in the FPGA... I don't want to affect the input impedance etc...

markus pushed to master at electronics/mini-poe-relay 2022-01-24 18:12:53 +01:00
794284486c kicad: Update TX/RX resistors
markus pushed to master at electronics/mini-poe-relay 2022-01-24 17:58:22 +01:00
c1064ea1fc kicad: Migrate to KiCad 6
markus commented on issue fpga/trashernet#5 2022-01-23 16:56:30 +01:00
DEMO: Implement MAC-layer test design

Implemented in d1150fb7dbc19668af1cf3892e3cdd381131fcd7.

markus closed issue fpga/trashernet#5 2022-01-23 16:56:30 +01:00
DEMO: Implement MAC-layer test design
markus opened issue fpga/trashernet#6 2022-01-23 16:55:43 +01:00
PHY:TX: Improve handling of NLP timing generation
markus pushed to master at fpga/trashernet 2022-01-23 16:51:52 +01:00
a9039a175c phy+mac: Improve interface
4a39c3d638 phy: Notify that the end-of-packet has been accepted
d1150fb7db demo: Add MAC demo design
d1e0143c9d phy: Fix TX manchester encoding
1bcddf4273 phy: Improve NLP timeout accuracy
Compare 14 commits »
markus pushed to feature/mac at fpga/trashernet 2022-01-23 16:51:35 +01:00
a9039a175c phy+mac: Improve interface
4a39c3d638 phy: Notify that the end-of-packet has been accepted
d1150fb7db demo: Add MAC demo design
Compare 3 commits »
markus commented on issue fpga/trashernet#5 2022-01-23 16:02:03 +01:00
DEMO: Implement MAC-layer test design

TX fixed in d1e0143c9dd6bb9c893d8fa4a185f3900d45463e.

markus pushed to feature/mac at fpga/trashernet 2022-01-23 16:01:29 +01:00
d1e0143c9d phy: Fix TX manchester encoding
1bcddf4273 phy: Improve NLP timeout accuracy
Compare 2 commits »
markus commented on issue fpga/trashernet#5 2022-01-22 20:50:22 +01:00
DEMO: Implement MAC-layer test design

RX works pretty much flawlessly in afb545cd021961aee6f4d66259116d194454465e, TX proves to be a little more difficult... not sure why yet, might be a HW issue.