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fpga: bench: Fix top level clock pin name

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This commit is contained in:
Markus Koch 2024-09-26 20:03:05 +02:00
parent 3ecc6a4ed1
commit 0545769bcd
1 changed files with 1 additions and 1 deletions
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fpga/hdl/bench/bench_top_manual.vhd
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@ -73,7 +73,7 @@ begin
top_inst : entity design.top top_inst : entity design.top
port map( port map(
clk_50m => clk, clk_in => clk,
uart_tx => uart_txd, uart_tx => uart_txd,
uart_rx => uart_rxd, uart_rx => uart_rxd,
eth_rx_p => rx_p, eth_rx_p => rx_p,