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fpga: uart_wb: Latch received byte to allow late retrieval of data

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Else, the CPU would get the part old / half current byte. This
enables boot loader baud rates in excess of 19200 baud.
This commit is contained in:
Markus Koch 2024-08-09 11:29:26 +02:00
parent e561c31691
commit 876693ca5f
1 changed files with 3 additions and 1 deletions
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4
fpga/hdl/design/uart_wb.vhd
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@ -41,6 +41,7 @@ architecture rtl of uart_wb is
signal status_register : std_logic_vector(31 downto 0); signal status_register : std_logic_vector(31 downto 0);
signal in_data : std_logic_vector(7 downto 0); signal in_data : std_logic_vector(7 downto 0);
signal in_data_latched : std_logic_vector(in_data'range);
signal in_data_valid : std_logic; signal in_data_valid : std_logic;
signal in_data_available : std_logic; signal in_data_available : std_logic;
@ -104,7 +105,7 @@ begin
out_data <= wb_i.dat(out_data'range); out_data <= wb_i.dat(out_data'range);
out_data_valid <= '1'; out_data_valid <= '1';
else else
wb_o.dat <= x"000000" & in_data; wb_o.dat <= x"000000" & in_data_latched;
in_data_available <= '0'; in_data_available <= '0';
end if; end if;
end if; end if;
@ -112,6 +113,7 @@ begin
if in_data_valid then if in_data_valid then
in_data_available <= '1'; in_data_available <= '1';
in_data_latched <= in_data;
end if; end if;
end if; end if;
end process wb_if; end process wb_if;