122 lines
3.2 KiB
VHDL
122 lines
3.2 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.all;
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entity bench_fifo_block is
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end entity bench_fifo_block;
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architecture RTL of bench_fifo_block is
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signal clk : std_logic;
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signal rst_a : std_logic;
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signal clr : std_logic;
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signal data_in : std_logic_vector(7 downto 0);
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signal write : std_logic;
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signal commit : std_logic;
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signal abort : std_logic;
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signal full : std_logic;
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signal data_out : std_logic_vector(data_in'range);
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signal data_first : std_logic;
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signal empty : std_logic;
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signal read : std_logic;
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begin
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fifo_block_inst : entity generics.fifo_block
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generic map(
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SIZE => 15
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)
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port map(
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clk => clk,
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rst_a => rst_a,
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clr => clr,
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data_in => data_in,
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write => write,
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commit => commit,
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abort => abort,
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full => full,
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data_out => data_out,
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data_first => data_first,
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empty => empty,
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read => read
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);
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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procedure push(constant data : in std_logic_vector(7 downto 0)) is
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begin
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data_in <= data;
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write <= '1';
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wait until rising_edge(clk);
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write <= '0';
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end procedure push;
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procedure pop(expected : std_logic_vector(7 downto 0); first : boolean) is
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begin
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read <= '1';
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wait until rising_edge(clk);
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report "Read data: " & to_hstring(data_out) & " - " & std_logic'image(data_first);
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assert (data_first = '1') = first report "Data first was " & std_logic'image(data_first) & " instead of " & boolean'image(first);
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assert data_out = expected report "Data is " & to_hstring(data_out) & ", should be " & to_hstring(expected) severity error;
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read <= '0';
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end procedure;
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procedure commit_data is
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begin
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commit <= '1';
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wait until rising_edge(clk);
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commit <= '0';
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end procedure commit_data;
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begin
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rst_a <= '1';
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clr <= '0';
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write <= '0';
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commit <= '0';
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abort <= '0';
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read <= '0';
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wait for 10 ns;
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rst_a <= '0';
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wait until rising_edge(clk);
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report "Pushing 5 items into FIFO";
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for i in 1 to 5 loop
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push(std_logic_vector(to_unsigned(i, data_in'length)));
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assert empty = '1' report "FIFO data present without commit";
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end loop;
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report "Committing data";
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commit_data;
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wait until rising_edge(clk);
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assert empty = '0' report "Commit did not validate data";
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report "Reading data";
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for i in 1 to 1 loop
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pop(std_logic_vector(to_unsigned(i, data_in'length)), i = 1);
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end loop;
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std.env.stop(0);
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wait;
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end process test;
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end architecture RTL;
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