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5 changed files with 54 additions and 192 deletions
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52
bench/bench_flashrom_controller.vhd
View File

@ -39,8 +39,8 @@ architecture rtl of bench_flashrom_controller is
signal status_update_stb : std_logic; signal status_update_stb : std_logic;
signal status : std_logic_vector(7 downto 0); signal status : std_logic_vector(7 downto 0);
signal info : std_logic_vector(31 downto 0); signal info : std_logic_vector(31 downto 0);
signal data_in : std_logic_vector(7 downto 0) := x"00"; signal data_in : std_logic_vector(7 downto 0);
signal data_in_next : std_logic; signal data_in_valid : std_logic;
signal data_out : std_logic_vector(7 downto 0); signal data_out : std_logic_vector(7 downto 0);
signal data_out_valid : std_logic; signal data_out_valid : std_logic;
signal spi_si : std_logic; signal spi_si : std_logic;
@ -50,7 +50,7 @@ architecture rtl of bench_flashrom_controller is
signal spi_cs_n : std_logic; signal spi_cs_n : std_logic;
signal spi_wp_n : std_logic; signal spi_wp_n : std_logic;
signal spi_busy : std_logic; signal spi_busy : std_logic;
signal spi_clk_cnt : integer := 0; signal spi_clk_cnt : integer := 0;
begin begin
DataFlash_inst : entity work.DataFlash DataFlash_inst : entity work.DataFlash
@ -83,7 +83,7 @@ begin
status => status, status => status,
info => info, info => info,
data_in => data_in, data_in => data_in,
data_in_next => data_in_next, data_in_valid => data_in_valid,
data_out => data_out, data_out => data_out,
data_out_valid => data_out_valid, data_out_valid => data_out_valid,
spi_si => spi_si, spi_si => spi_si,
@ -107,11 +107,8 @@ begin
--testbench --testbench
bench : process is bench : process is
begin begin
rst <= '1'; rst <= '1';
clr <= '0'; clr <= '0';
status_update_stb <= '0';
load_stb <= '0';
page <= (others => '0');
wait for 10 ns * 2; wait for 10 ns * 2;
wait until (rising_edge(clk)); wait until (rising_edge(clk));
rst <= '0'; rst <= '0';
@ -120,40 +117,29 @@ begin
-- bench code here -- bench code here
wait until ready = '1'; wait until ready = '1';
strobe(status_update_stb); strobe(load_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
wait for 100 us;
strobe(sync_stb); -- Make sure background_op_enable is '1' in device model (power up delay)
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
wait until spi_busy = '1';
wait for 100 us;
strobe(status_update_stb);
wait until ready = '1'; wait until ready = '1';
strobe(load_stb); strobe(load_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(load_stb);
wait; wait;
end process bench; end process bench;
spiclkcounter : process is spiclkcounter : process is
begin begin
wait until data_out_valid = '1'; wait until spi_sck = '1';
spi_clk_cnt <= spi_clk_cnt + 1; spi_clk_cnt <= spi_clk_cnt + 1;
end process spiclkcounter; end process spiclkcounter;
data_provider : process is
begin
wait until data_in_next = '1';
--wait until data_in_next = '1';
data_in <= std_logic_vector(unsigned(data_in) + 1);
end process data_provider;
end architecture rtl; end architecture rtl;

69
cores/flashrom-wb/flashrom_controller.vhd
View File

@ -21,7 +21,7 @@ entity flashrom_controller is
-- Data IF -- Data IF
data_in : in std_logic_vector(7 downto 0); data_in : in std_logic_vector(7 downto 0);
data_in_next : out std_logic; data_in_valid : in std_logic;
data_out : out std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0);
data_out_valid : out std_logic; data_out_valid : out std_logic;
@ -37,10 +37,10 @@ end entity flashrom_controller;
architecture RTL of flashrom_controller is architecture RTL of flashrom_controller is
constant spif_max_word_length : integer := 32; constant spif_max_word_length : integer := 32;
constant max_dummy_bits : integer := 63; constant max_dummy_bits : integer := 16;
constant bootup_delay : integer := 4000; constant bootup_delay : integer := 4000;
type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, WRITEPAGE, IDLE); type state_t is (INIT, GETINFO, GETSTATUS, IDLE);
signal state : state_t; signal state : state_t;
signal spif_data_in_valid : std_logic; signal spif_data_in_valid : std_logic;
@ -54,7 +54,6 @@ architecture RTL of flashrom_controller is
signal words_sent : integer range 0 to 511; signal words_sent : integer range 0 to 511;
signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits; signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits;
signal spif_transmission_active : std_logic; signal spif_transmission_active : std_logic;
signal command_is_latched : boolean;
begin begin
spi_wp_n <= '1'; spi_wp_n <= '1';
@ -82,15 +81,14 @@ begin
transmission_active => spif_transmission_active); transmission_active => spif_transmission_active);
flashrom_controller_p : process(clk, rst) is flashrom_controller_p : process(clk, rst) is
variable write_cnt : integer range 0 to bootup_delay; variable temp_cnt : integer range 0 to bootup_delay;
variable done : boolean; variable done : boolean;
procedure default_state is procedure default_state is
begin begin
spi_reset_n <= '1'; spi_reset_n <= '1';
spif_data_in_valid <= '0'; spif_data_in_valid <= '0';
done := false; done := false;
command_is_latched <= false;
end procedure default_state; end procedure default_state;
procedure reset_state is procedure reset_state is
@ -99,35 +97,34 @@ begin
state <= INIT; state <= INIT;
spi_reset_n <= '0'; spi_reset_n <= '0';
words_sent <= 0; words_sent <= 0;
write_cnt := 0;
spif_data_in <= (others => '0'); spif_data_in <= (others => '0');
spif_data_in_length <= 0; spif_data_in_length <= 0;
spif_data_out_length <= 0; spif_data_out_length <= 0;
spif_data_out_dummy_bits <= 0; spif_data_out_dummy_bits <= 0;
write_cnt := 0; temp_cnt := 0;
end procedure reset_state; end procedure reset_state;
procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector) is procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector(31 downto 0)) is
begin begin
spif_data_in_length <= data_in_length; spif_data_in_length <= data_in_length;
spif_data_out_length <= data_out_length; spif_data_out_length <= data_out_length;
spif_data_out_dummy_bits <= data_out_dummy_bits; spif_data_out_dummy_bits <= data_out_dummy_bits;
spif_data_in_valid <= '1'; spif_data_in_valid <= '1';
spif_data_in <= data_in & padBits(spif_data_in, data_in); spif_data_in <= data_in;
if write_cnt = nTxWords then if temp_cnt = nTxWords then
spif_data_in_valid <= '0'; spif_data_in_valid <= '0';
elsif spif_data_next = '1' then elsif spif_data_next = '1' then
write_cnt := write_cnt + 1; temp_cnt := temp_cnt + 1;
end if; end if;
if spif_data_out_valid = '1' and (write_cnt = nTxWords) then if spif_data_out_valid = '1' then
spif_data_in_valid <= '0'; spif_data_in_valid <= '0';
done := true; done := true;
state <= IDLE; state <= IDLE;
write_cnt := 0; temp_cnt := 0;
end if; end if;
end procedure run_command_single; end procedure run_command_single;
@ -142,57 +139,33 @@ begin
case state is case state is
when INIT => when INIT =>
words_sent <= 0; words_sent <= 0;
if write_cnt = bootup_delay then if temp_cnt = bootup_delay then
write_cnt := 0; temp_cnt := 0;
state <= GETINFO; state <= GETINFO;
else else
write_cnt := write_cnt + 1; temp_cnt := temp_cnt + 1;
end if; end if;
when GETINFO => -- TODO: In simulation I can only call this command once?! when GETINFO => -- TODO: In simulation I can only call this command once?!
run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID); run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID));
if done then if done then
info <= spif_data_out; info <= spif_data_out;
end if; end if;
when IDLE => when IDLE =>
write_cnt := 0; temp_cnt := 0;
if status_update_stb = '1' then if status_update_stb = '1' then
state <= GETSTATUS; state <= GETSTATUS;
end if; end if;
if load_stb = '1' then if load_stb = '1' then --debug only
state <= LOADPAGE; state <= GETINFO;
end if;
if sync_stb = '1' then
state <= WRITEPAGE;
end if; end if;
when GETSTATUS => when GETSTATUS =>
run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS); run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS));
if done then if done then
status <= spif_data_out(7 downto 0); status <= spif_data_out(7 downto 0);
end if; end if;
when LOADPAGE =>
run_command_single(32, 8, 34, 258, FLASHROM_COMMAND_CONT_ARRAY_READ & page);
if spif_data_next = '1' or command_is_latched then
command_is_latched <= true;
spif_data_in_length <= 8;
spif_data_in <= (others => '0');
end if;
if done then
report "Load page done." severity note;
end if;
when WRITEPAGE =>
run_command_single(32, 8, 34, 257, FLASHROM_COMMAND_WRITE_THROUGH_1 & page);
if spif_data_next = '1' or command_is_latched then
command_is_latched <= true;
spif_data_in_length <= 8;
spif_data_in <= data_in & padBits(spif_data_in, data_in);
end if;
end case; end case;
end if; end if;
end if; end if;
end process flashrom_controller_p; end process flashrom_controller_p;
ready <= '1' when state = IDLE else '0'; ready <= '1' when state = IDLE else '0';
data_out <= spif_data_out(7 downto 0);
data_out_valid <= spif_data_out_valid when state = LOADPAGE else '0';
data_in_next <= spif_data_next when (state = WRITEPAGE) and command_is_latched else '0';
end architecture RTL; end architecture RTL;

2
cores/flashrom-wb/flashrom_pkg.vhd
View File

@ -6,8 +6,6 @@ package flashrom_pkg is
constant FLASHROM_ADDR_WIDTH : integer := 12; constant FLASHROM_ADDR_WIDTH : integer := 12;
constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7"; constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7";
constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B";
constant FLASHROM_COMMAND_WRITE_THROUGH_1 : std_logic_vector(7 downto 0) := x"82";
function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector;
end package flashrom_pkg; end package flashrom_pkg;

36
cores/flashrom-wb/flashrom_spi.vhd
View File

@ -45,7 +45,6 @@ architecture RTL of flashrom_spi is
signal oneBitRead : std_logic; signal oneBitRead : std_logic;
signal pseudoEdge : boolean; signal pseudoEdge : boolean;
signal dummy_passed : boolean; signal dummy_passed : boolean;
signal prevent_retrig : boolean;
begin begin
toSpi : process(clk, rst) is toSpi : process(clk, rst) is
procedure default_state is procedure default_state is
@ -78,28 +77,20 @@ begin
else else
case state is case state is
when IDLE => when IDLE =>
prevent_retrig <= false; delayCycle <= '0';
delayCycle <= '0'; spi_sck <= '0';
spi_sck <= '0'; oneBitRead <= '0';
oneBitRead <= '0'; dummy_passed <= false;
dummy_passed <= false; data_out <= (others => '0');
data_out <= (others => '0'); if data_in_valid = '1' then
if ckDiv = clk_divider - 2 then -- ensures cs inactive time between transactions state <= TX;
if data_in_valid = '1' then bitCounter <= 0;
ckDiv <= 0; bitCounterIn <= 0;
state <= TX; data_in_length_i <= 0;
bitCounter <= 0; pseudoEdge <= true;
bitCounterIn <= 0;
data_in_length_i <= 0;
pseudoEdge <= true;
end if;
else
ckDiv <= ckDiv + 1;
end if; end if;
ckDiv <= 0;
when TX => when TX =>
if data_in_valid = '0' then
prevent_retrig <= true;
end if;
if ckDiv = clk_divider - 2 or pseudoEdge then if ckDiv = clk_divider - 2 or pseudoEdge then
ckDiv <= 0; ckDiv <= 0;
if not pseudoEdge then if not pseudoEdge then
@ -113,7 +104,7 @@ begin
if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data
if bitCounter = data_in_length_i then if bitCounter = data_in_length_i then
bitCounter <= 0; bitCounter <= 0;
if data_in_valid = '1' and not prevent_retrig then if data_in_valid = '1' then
shiftreg <= data_in; shiftreg <= data_in;
data_in_length_i <= data_in_length - 1; data_in_length_i <= data_in_length - 1;
data_out_length_i <= data_out_length - 1; data_out_length_i <= data_out_length - 1;
@ -149,7 +140,6 @@ begin
if delayCycle = '1' then if delayCycle = '1' then
spi_sck <= '0'; spi_sck <= '0';
state <= IDLE; state <= IDLE;
ckDiv <= 0;
end if; end if;
end if; end if;
end if; end if;

85
wave/flashrom_controller.do
View File

@ -1,85 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /bench_flashrom_controller/DataFlash_inst/RDYBSY
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/clk
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/rst
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/clr
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/ready
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/page
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/sync_stb
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/load_stb
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/status_update_stb
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/status
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/info
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_in_next
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_in
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_out
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_out_valid
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_si
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_so
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_sck
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_reset_n
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_cs_n
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_wp_n
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/state
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in_valid
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in_length
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_next
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_valid
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_length
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/words_sent
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_dummy_bits
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_transmission_active
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_max_word_length
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/max_dummy_bits
add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/bootup_delay
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clk_divider
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/max_word_length
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/max_dummy_bits
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clk
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/rst
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clr
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_si
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_so
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_sck
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_cs_n
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_valid
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_length
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_next
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_valid
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_length
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_dummy_bits
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/transmission_active
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/state
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/ckDiv
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/shiftreg
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/bitCounter
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/bitCounterIn
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_length_i
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_length_i
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/delayCycle
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/oneBitRead
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/pseudoEdge
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/dummy_passed
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {40873000 ps} 1} {{Cursor 2} {16507398 ps} 0} {{Cursor 3} {1785398 ps} 0}
quietly wave cursor active 2
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {105 us}