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265d1a80e1
...
9ff7421242
@ -39,8 +39,8 @@ architecture rtl of bench_flashrom_controller is
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signal status_update_stb : std_logic;
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signal status : std_logic_vector(7 downto 0);
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signal info : std_logic_vector(31 downto 0);
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signal data_in : std_logic_vector(7 downto 0) := x"00";
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signal data_in_next : std_logic;
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signal data_in : std_logic_vector(7 downto 0);
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signal data_in_valid : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_out_valid : std_logic;
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signal spi_si : std_logic;
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@ -50,7 +50,7 @@ architecture rtl of bench_flashrom_controller is
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signal spi_cs_n : std_logic;
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signal spi_wp_n : std_logic;
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signal spi_busy : std_logic;
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signal spi_clk_cnt : integer := 0;
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signal spi_clk_cnt : integer := 0;
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begin
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DataFlash_inst : entity work.DataFlash
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@ -83,7 +83,7 @@ begin
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status => status,
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info => info,
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data_in => data_in,
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data_in_next => data_in_next,
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data_in_valid => data_in_valid,
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data_out => data_out,
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data_out_valid => data_out_valid,
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spi_si => spi_si,
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@ -107,11 +107,8 @@ begin
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--testbench
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bench : process is
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begin
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rst <= '1';
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clr <= '0';
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status_update_stb <= '0';
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load_stb <= '0';
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page <= (others => '0');
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rst <= '1';
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clr <= '0';
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wait for 10 ns * 2;
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wait until (rising_edge(clk));
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rst <= '0';
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@ -120,40 +117,29 @@ begin
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-- bench code here
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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wait for 100 us;
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strobe(sync_stb); -- Make sure background_op_enable is '1' in device model (power up delay)
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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wait until spi_busy = '1';
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wait for 100 us;
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strobe(status_update_stb);
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strobe(load_stb);
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wait until ready = '1';
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strobe(load_stb);
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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strobe(load_stb);
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wait;
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end process bench;
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spiclkcounter : process is
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begin
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wait until data_out_valid = '1';
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wait until spi_sck = '1';
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spi_clk_cnt <= spi_clk_cnt + 1;
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end process spiclkcounter;
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data_provider : process is
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begin
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wait until data_in_next = '1';
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--wait until data_in_next = '1';
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data_in <= std_logic_vector(unsigned(data_in) + 1);
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end process data_provider;
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end architecture rtl;
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@ -21,7 +21,7 @@ entity flashrom_controller is
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-- Data IF
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data_in : in std_logic_vector(7 downto 0);
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data_in_next : out std_logic;
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data_in_valid : in std_logic;
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data_out : out std_logic_vector(7 downto 0);
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data_out_valid : out std_logic;
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@ -37,10 +37,10 @@ end entity flashrom_controller;
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architecture RTL of flashrom_controller is
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constant spif_max_word_length : integer := 32;
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constant max_dummy_bits : integer := 63;
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constant max_dummy_bits : integer := 16;
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constant bootup_delay : integer := 4000;
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type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, WRITEPAGE, IDLE);
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type state_t is (INIT, GETINFO, GETSTATUS, IDLE);
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signal state : state_t;
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signal spif_data_in_valid : std_logic;
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@ -54,7 +54,6 @@ architecture RTL of flashrom_controller is
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signal words_sent : integer range 0 to 511;
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signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits;
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signal spif_transmission_active : std_logic;
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signal command_is_latched : boolean;
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begin
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spi_wp_n <= '1';
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@ -82,15 +81,14 @@ begin
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transmission_active => spif_transmission_active);
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flashrom_controller_p : process(clk, rst) is
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variable write_cnt : integer range 0 to bootup_delay;
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variable done : boolean;
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variable temp_cnt : integer range 0 to bootup_delay;
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variable done : boolean;
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procedure default_state is
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begin
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spi_reset_n <= '1';
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spif_data_in_valid <= '0';
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done := false;
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command_is_latched <= false;
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end procedure default_state;
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procedure reset_state is
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@ -99,35 +97,34 @@ begin
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state <= INIT;
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spi_reset_n <= '0';
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words_sent <= 0;
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write_cnt := 0;
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spif_data_in <= (others => '0');
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spif_data_in_length <= 0;
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spif_data_out_length <= 0;
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spif_data_out_dummy_bits <= 0;
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write_cnt := 0;
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temp_cnt := 0;
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end procedure reset_state;
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procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector) is
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procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector(31 downto 0)) is
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begin
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spif_data_in_length <= data_in_length;
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spif_data_out_length <= data_out_length;
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spif_data_out_dummy_bits <= data_out_dummy_bits;
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spif_data_in_valid <= '1';
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spif_data_in <= data_in & padBits(spif_data_in, data_in);
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spif_data_in <= data_in;
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if write_cnt = nTxWords then
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if temp_cnt = nTxWords then
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spif_data_in_valid <= '0';
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elsif spif_data_next = '1' then
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write_cnt := write_cnt + 1;
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temp_cnt := temp_cnt + 1;
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end if;
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if spif_data_out_valid = '1' and (write_cnt = nTxWords) then
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if spif_data_out_valid = '1' then
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spif_data_in_valid <= '0';
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done := true;
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state <= IDLE;
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write_cnt := 0;
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temp_cnt := 0;
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end if;
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end procedure run_command_single;
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@ -142,57 +139,33 @@ begin
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case state is
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when INIT =>
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words_sent <= 0;
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if write_cnt = bootup_delay then
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write_cnt := 0;
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state <= GETINFO;
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if temp_cnt = bootup_delay then
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temp_cnt := 0;
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state <= GETINFO;
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else
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write_cnt := write_cnt + 1;
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temp_cnt := temp_cnt + 1;
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end if;
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when GETINFO => -- TODO: In simulation I can only call this command once?!
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run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID);
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run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID));
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if done then
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info <= spif_data_out;
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end if;
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when IDLE =>
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write_cnt := 0;
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temp_cnt := 0;
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if status_update_stb = '1' then
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state <= GETSTATUS;
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end if;
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if load_stb = '1' then
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state <= LOADPAGE;
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end if;
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if sync_stb = '1' then
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state <= WRITEPAGE;
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if load_stb = '1' then --debug only
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state <= GETINFO;
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end if;
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when GETSTATUS =>
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run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS);
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run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS));
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if done then
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status <= spif_data_out(7 downto 0);
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end if;
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when LOADPAGE =>
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run_command_single(32, 8, 34, 258, FLASHROM_COMMAND_CONT_ARRAY_READ & page);
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if spif_data_next = '1' or command_is_latched then
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command_is_latched <= true;
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spif_data_in_length <= 8;
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spif_data_in <= (others => '0');
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end if;
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if done then
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report "Load page done." severity note;
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end if;
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when WRITEPAGE =>
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run_command_single(32, 8, 34, 257, FLASHROM_COMMAND_WRITE_THROUGH_1 & page);
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if spif_data_next = '1' or command_is_latched then
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command_is_latched <= true;
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spif_data_in_length <= 8;
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spif_data_in <= data_in & padBits(spif_data_in, data_in);
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end if;
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end case;
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end if;
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end if;
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end process flashrom_controller_p;
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ready <= '1' when state = IDLE else '0';
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data_out <= spif_data_out(7 downto 0);
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data_out_valid <= spif_data_out_valid when state = LOADPAGE else '0';
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data_in_next <= spif_data_next when (state = WRITEPAGE) and command_is_latched else '0';
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end architecture RTL;
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@ -6,8 +6,6 @@ package flashrom_pkg is
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constant FLASHROM_ADDR_WIDTH : integer := 12;
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constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
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constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7";
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constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B";
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constant FLASHROM_COMMAND_WRITE_THROUGH_1 : std_logic_vector(7 downto 0) := x"82";
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function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector;
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end package flashrom_pkg;
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@ -45,7 +45,6 @@ architecture RTL of flashrom_spi is
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signal oneBitRead : std_logic;
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signal pseudoEdge : boolean;
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signal dummy_passed : boolean;
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signal prevent_retrig : boolean;
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begin
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toSpi : process(clk, rst) is
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procedure default_state is
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@ -78,28 +77,20 @@ begin
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else
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case state is
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when IDLE =>
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prevent_retrig <= false;
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delayCycle <= '0';
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spi_sck <= '0';
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oneBitRead <= '0';
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dummy_passed <= false;
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data_out <= (others => '0');
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if ckDiv = clk_divider - 2 then -- ensures cs inactive time between transactions
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if data_in_valid = '1' then
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ckDiv <= 0;
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state <= TX;
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bitCounter <= 0;
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bitCounterIn <= 0;
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data_in_length_i <= 0;
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pseudoEdge <= true;
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end if;
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else
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ckDiv <= ckDiv + 1;
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delayCycle <= '0';
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spi_sck <= '0';
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oneBitRead <= '0';
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dummy_passed <= false;
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data_out <= (others => '0');
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if data_in_valid = '1' then
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state <= TX;
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bitCounter <= 0;
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bitCounterIn <= 0;
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data_in_length_i <= 0;
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pseudoEdge <= true;
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end if;
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ckDiv <= 0;
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when TX =>
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if data_in_valid = '0' then
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prevent_retrig <= true;
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end if;
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if ckDiv = clk_divider - 2 or pseudoEdge then
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ckDiv <= 0;
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if not pseudoEdge then
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@ -113,7 +104,7 @@ begin
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if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data
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if bitCounter = data_in_length_i then
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bitCounter <= 0;
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if data_in_valid = '1' and not prevent_retrig then
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if data_in_valid = '1' then
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shiftreg <= data_in;
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data_in_length_i <= data_in_length - 1;
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data_out_length_i <= data_out_length - 1;
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@ -149,7 +140,6 @@ begin
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if delayCycle = '1' then
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spi_sck <= '0';
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state <= IDLE;
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ckDiv <= 0;
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end if;
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end if;
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end if;
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@ -1,85 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /bench_flashrom_controller/DataFlash_inst/RDYBSY
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/clk
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/rst
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/clr
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/ready
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/page
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/sync_stb
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/load_stb
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/status_update_stb
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/status
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/info
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_in_next
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_in
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_out
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/data_out_valid
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_si
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_so
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_sck
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_reset_n
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_cs_n
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spi_wp_n
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/state
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in_valid
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_in_length
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_next
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_valid
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_length
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/words_sent
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_data_out_dummy_bits
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_transmission_active
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/spif_max_word_length
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/max_dummy_bits
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add wave -noupdate /bench_flashrom_controller/flashrom_controller_inst/bootup_delay
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clk_divider
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/max_word_length
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/max_dummy_bits
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clk
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/rst
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/clr
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_si
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_so
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_sck
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/spi_cs_n
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_valid
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_length
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_next
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_valid
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_length
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add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_dummy_bits
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/transmission_active
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/state
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/ckDiv
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/shiftreg
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/bitCounter
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/bitCounterIn
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_in_length_i
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/data_out_length_i
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/delayCycle
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/oneBitRead
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/pseudoEdge
|
||||
add wave -noupdate -group spiphy /bench_flashrom_controller/flashrom_controller_inst/flashrom_spi_inst/dummy_passed
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {40873000 ps} 1} {{Cursor 2} {16507398 ps} 0} {{Cursor 3} {1785398 ps} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {105 us}
|
||||
Loading…
Reference in New Issue
Block a user