misc: Allow dynamic length for synchronizer
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@ -3,6 +3,9 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity synchronizer is
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generic(
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SIZE : integer := 3
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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@ -12,7 +15,7 @@ entity synchronizer is
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end entity synchronizer;
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architecture RTL of synchronizer is
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signal sr : std_logic_vector(2 downto 0);
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signal sr : std_logic_vector(SIZE - 1 downto 0);
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begin
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sync : process(clk, rst) is
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begin
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